Questions about cache

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Questions about cache

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adrianonea
Contributor III

I am using S32R274 went through the reference manual and I have the following things I would like to clarify about the cache.

1. There is a cache invalidation mechanism which will force the next read to be from RAM. Is there a "flush". Is a flush required or will the hardware automatically update the SRAM independently?

2. The cash can be enabled/disabled for certain address ranges from both SMPU and the MMU. Why would you use one vs another one? I assume MMU is only relevant for the attached processor as one of the reasons.

3. Cash Invalidation.  Data Cash can be invalidated by writing a 1 in the DCINV from the L1CSR0 register or to L1FINV0. When would you use one vs another one? What is the differnce.

The manual does not explain what values go into CSET bits.

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3 Replies

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lukaszadrapa
NXP TechSupport
NXP TechSupport

Hi Adrian,

1. If the cache is configured in write-through mode then all the data are immediately written also to memory (SRAM). That means it is not required to flush the cache because data are coherent.
 If it is configured in copy-back mode, it is necessary to flush the cache because cache invalidation doesn’t do that. I can see in the reference manual for S32R274 that there’s no support for flush by L1FINV0/1 registers, so you have to use dcbf instruction.

2. There’s MPU (sometimes called CMPU) on this device instead of MMU. MMU has been used on MPC55xx, MPC56xx devices and on MPC5777C. On other MPC57xx and on S32R, there’s MPU.
MPU is implemented on core, so its settings have effect only for core access.
SMPU (System MPU) is implemented on crossbar switch, so its settings have effect for all masters.
That means you need to configure both MPU and SMPU appropriately.

3. DCINV bit will invalidate whole data cache. If you use L1FINV0, it will invalidate only Way and Set which you wrote to this register.
There’s 2-way set cache: 4KB data cache on e200z4 core and 16KB data cache on e200z7 core.
One cache line is 32 bytes, so there are 128 sets on e200z4 and 512 sets on e200z7.
That means the CWAY can be set 0 or 1 and CSET 0-63 on e200z4. On e200z7, the CSET can be set to 0-255.

Regards,

Lukas

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152 Views
adrianonea
Contributor III

Thank you Lukasz,

Can I please get a few more details.1. How do you configure S32R274 for write through?2. If I want a memory region to not be cached is it enough if I configure that in SMPU only or do I have to configure both the SMPU and the MPU? Sorry to keep asking. I can probably test myself but memory consistency bugs are hard to debug and sometimes they don't show up.3 How would you know which way to invalidate for a certain variable/memory region? You can probably work out the cache set where the memory is potentially kept but have no idea how to work out the way. Do you have any code samples/

From: lukaszadrapa <admin@community.nxp.com>

To: adrian onea <adrian_onea@yahoo.com>

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Re: Questions about cache

reply from Lukas Zadrapa in MPC5xxx - View the full discussionHi Adrian, 1. If the cache is configured in write-through mode then all the data are immediately written also to memory (SRAM). That means it is not required to flush the cache because data are coherent.

 If it is configured in copy-back mode, it is necessary to flush the cache because cache invalidation doesn’t do that. I can see in the reference manual for S32R274 that there’s no support for flush by L1FINV0/1 registers, so you have to use dcbf instruction. 2. There’s MPU (sometimes called CMPU) on this device instead of MMU. MMU has been used on MPC55xx, MPC56xx devices and on MPC5777C. On other MPC57xx and on S32R, there’s MPU.

MPU is implemented on core, so its settings have effect only for core access.

SMPU (System MPU) is implemented on crossbar switch, so its settings have effect for all masters.

That means you need to configure both MPU and SMPU appropriately. 3. DCINV bit will invalidate whole data cache. If you use L1FINV0, it will invalidate only Way and Set which you wrote to this register.

There’s 2-way set cache: 4KB data cache on e200z4 core and 16KB data cache on e200z7 core.

One cache line is 32 bytes, so there are 128 sets on e200z4 and 512 sets on e200z7.

That means the CWAY can be set 0 or 1 and CSET 0-63 on e200z4. On e200z7, the CSET can be set to 0-255. Regards,Lukas

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152 Views
lukaszadrapa
NXP TechSupport
NXP TechSupport

1. How do you configure S32R274 for write through?

- I found out that this device supports ONLY write-through mode. So, there's no need to do flush at all.

2. If I want a memory region to not be cached is it enough if I configure that in SMPU only or do I have to configure both the SMPU and the MPU?

- If "cache inhibited" is configured in SMPU or in MPU or in both, it will be considered as cache inhibited. If you want to configure some areas as cacheable, then it must be enabled in both SMPU an MPU.

3 How would you know which way to invalidate for a certain variable/memory region?

- simply invalidate both ways.

Regards,

Lukas

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