Hi Jerry,
The MCU I'm working with is a MPC5643L, but the core is a e200z4, too, and both MCUs use the INTC as interrupt controller, so there should be no significant difference with respect to your question.
The interrupt system has two tiers. The CPU uses the IVORs as interrupt vectors. You may call this interrupt, trap or exception, that's just wording. The addresses of the interrupt service routines are stored as register values in the CPU (SPR 400++); some of the address bits are common to all service routines (another register, SPR 63, IVPR) and they must therefore be within a 64k memory page.
The second layer of interrupt handling is the handling of one particular IVOR, this is IVOR4, dedicated to the "External Interrupts". An External Interrupt is what is mostly referred to simply as interrupt; it's the interrupt raised by the many I/O devices. In the MPC, all device interrupts are a single interrupt on CPU level. The CPU will start any of these interrupts by a jump to the IVOR4 routine. This routine will at its beginning find out, which device caused the (external) interrupt and then decide for the right, particular interrupt handler.
The decision, which device caused the interrupt and which service routine to branch to, is widely hardware supported, there is the device INTC, which does most of the work. Effectively, the CPU just reads a register of the INTC to get the index of the causing device and translating this into a valid service routine address is a matter of a single machine instruction.
Or even less, the INTC supports the hardware vector mode, which enables direct fetch of an address on the bus.
However, all code samples I've seen so far use the software mode, where the CPU does do the address computation. The penalty is very little and this mode enables the SW to configure service routines at run-time. User code is enabled to define additional service routines to serve more I/O devices.
Because of the two-tier interrupt handling a typical MPC sample will do interrupt setup twice:
- It shall install all CPU interrupts (the IVORs) but this will mostly be
dummies, not doing anything than spinning forever at the same
instruction (so that the debugger can indicate the problem after a
break). The big exception is IVOR4. A typical sample will put here the
address of an interrupt service routine for all the External Interrupts
- The interrupt service routine for the External Interrupts will likely
implement the SW mode and this is typically offered to the user as a
table of function pointers, one table entry for each I/O device.
This table can be pre-filled or there is an API to set an entry at
run-time. The setup of this table is likely what you expect as interrupt
configuration
The association of the table entries with actual I/O devices is hard-wired in the MCU HW and can't be changed by SW. You will find a table in the reference manual, see device INTC. And anyway, you won't safely be able to work with interrupts and their configuration without reading this section of the MCU ref manual.
Regards,
Peter
