Question about the MPC5748G ULPI0_Data interface output

[H-chips]

Dear NXP Community,

  When I used the USB0 interface of MPC5748G, after enabling the clock and interface, I used the oscilloscope to detect the potential of ULPI0_Data[0:7] as follows:

ULPI0_Data[0]: 3.3v
ULPI0_Data[1]: 0v
ULPI0_Data[2]: 3.3v
ULPI0_Data[3]: 0v
ULPI0_Data[4]: 0v
ULPI0_Data[5]: 0v
ULPI0_Data[6]: 1v
ULPI0_Data[7]: 1v

  These levels do not change, which is a stable continuous voltage waveform. I think only enable the case of the clock, should be idle state, idle state is Low? Is there a problem here?

  Second, is the voltage at ULPI0_Data[6:7] a normal voltage?

  All of these outputs are LOW until the clock is enabled.

  Looking forward to your help!

H-chips

[PetrS]

Hi,

ULPI0_Data are bidirectional pins, question could be who is driving it. 1V does not seems to be correct voltage. Is there any device connected to ULPI interface? What about other signals (DIR, NXT, STP)?
The RM indicates DIR pin should have weak pull down enabled, so check that.

BR, Petr

[H-chips]

Hello, I have found that Data[6] and Data[7] are short-circuited, resulting in both performances of 1V.

But the new problem is that after sending the TXD CMD, the USB controller (USB3340) does not pull the NXT up. What are the possibilities?

[PetrS · Accepted solution]

Hi,

MCU drives TX CMD on data lines but NXT is driven by PHY, so if TX CMD is proper, rather consult USB3340 datasheet for detailed info.

BR, Petr

[H-chips]

Ok, thank you very much, I will check this topic.

[H-chips]

Thank you very much for your answer. I will check it over here.