Hello, does the Quadrature Decode (QDEC) Mode(for count and direction encoders type) of the eMIOS module in the MPC5777c processor support simultaneous counting on both the rising and falling edges by setting the EDSEL bit, and generating an event when the internal counter matches the A1 register?
As shown by the underlined part in the above picture, is the EDSEL bit valid in the Quadrature Decode (QDEC) Mode (for count and direction encoders type)?
Hello,
does the Quadrature Decode (QDEC) Mode(for count and direction encoders type) of the eMIOS module in the MPC5777c processor support simultaneous counting on both the rising and falling edges by setting the EDSEL bit,
No. as EDSEL bit describes, the implementation for each mode is state in mode description.
In QDEC mode (mode 0x0D), the eMIOS hardware automatically handles quadrature decoding, including edge detection and direction.
The QDEC mode uses two input signals (A and B) and interprets their transitions to determine both count and direction. This logic is independent of the EDSEL bit.
Therefore, setting EDSEL has no effect in QDEC mode—it is ignored by the hardware.
Best regards,
Peter
