Problem of access FIFO of CTU with it works at dual conversion mode

cancel
Showing results for 
Search instead for 
Did you mean: 

Problem of access FIFO of CTU with it works at dual conversion mode

718 Views
maxlee
Contributor II

Hi,

I'm trying to test the FlexPWM- CTU-ADC program. I configured the CTU for triggering on FlexPWM MRS and generate the Trigger0 to send 3 ADC dual conversion commands, and the results are saved in FIFO0. I set the threshold of FIFO0 to 5 and enable the FIFO0 overflow interrupt. Here is my code.

Configuration of CTU

#define CTU0_TGSISR 0x00000001 /* Input 0 Rising Edge Enable - FlexPWM0_MRS */
#define CTU0_TGSCR 0x0000          /* Triggered Mode */
#define CTU0_T0CR 0x0000             /* ADC and SGEN - same time with MRS*/
#define CTU0_TGSCCR 0x3E80       /* TGS Counter Compare Value - 16000 DEC - 100us */
#define CTU0_CLCR1 0x00000000   /* Trigger 0 Commands List 1st command address */
#define CTU0_THCR1 0x00000065   /* T0_E - T0_T2E - T0_ADCE */
#define CTU0_COTR 0x0064             /* Control ON-Time and Guard Time for external trigger */
#define CTU0_CTU0CR 0x0003         /* General Reload Enable - TGS Input Selection Register Reload Enable */
#define CTU0_CLR0 0x218B              /* PhaseA current ADC0_CH11 - PhaseB current ADC1_CH12 - FIFO_0 */
#define CTU0_CLR1 0x21C1              /* DC bus current ADC0_CH1 - DC bus voltage ADC1_CH14 - FIFO_0 */
#define CTU0_CLR2 0x20C0              /* Resolver sin ADC0_CH0 - Pot ADC1_CH6 - FIFO_0 */
#define CTU0_CLR3 0x4000               /* Last command */
#define CTU0_FTH 0x0005                 /* FIFO_0 threshold is 5 to accept 6 ADC results */
#define CTU0_FCR 0x0004                 /* FIFO 0 threshold overflow interrupt enable */

FIFO0_ISR

void FIFO0_ISR(void)
{
SIUL2.GPDO[42].R = 1;
uint32_t fifo_status;

fifo_status = CTU_0.FST.R & 0xf;

if (fifo_status == 4) // if overflow
{
Result[0] = (uint32_t)CTU_0.FR[0].R;
Result[1] = (uint32_t)CTU_0.FL[0].R;
Result[2] = (uint32_t)CTU_0.FR[0].R;
Result[3] = (uint32_t)CTU_0.FL[0].R;
Result[4] = (uint32_t)CTU_0.FR[0].R;
Result[5] = (uint32_t)CTU_0.FL[0].R;
FlexPWM_0.SUB[0].VAL3.R = (uint16_t)(Result[5] & 0xfff);      // use the value of pot to change the duty of PWM

FlexPWM_0.MCTRL.B.LDOK = 0x7;

CTU_0.CR.B.GRE = 1; // CTU General Reload Enable
}

if (fifo_status == 8) // if overrun
{
CTU_0.FST.R = 8; // clear overrun flag
}

SIUL2.GPDO[42].R = 0;

}

According to my configuration, there will be 6 ADC results saved in CTU_FIFO0 every time the overflow interrupt happened. And the last result entered in FIFO0 should be the value of the Pot(PE12).

When I debug the project, I find the FIFO0_FR0 has the result of ADC0_CH11 and FIFO0_FL0 has the result of ADC1_CH12, these are conform to my configuration. And somehow I found the overflow flag, overrun flag and full flag of FIFO0 are all set via the EmbSysRegister. And the PWM duty didn't change as I want.

I don't know whether I read the FIFO correctly. I'm quite confused about this FIFO and I want to know whether there are some methods to check the correctness of my code.

Thanks for any help.

Best regards,

Max Lee

Tags (4)
4 Replies

281 Views
petervlna
NXP Employee
NXP Employee

Hi Max,

There is for sure some missconfiguration in your code.

As the CTU FIFO is commonly used by customers.

We have posted reference example for it here on forum:

Example MPC5744P FlexPWM CTU ADC synchronization 

And I have also wrote and document for this thema:

https://community.nxp.com/docs/DOC-102559 

MPC5643L implementation is same for MPC5744P. So you can use this document.

After studying this, If you still struggle feel free to share your compiled code (even binary output file is ok), so I can check where is your issue on my board.

Peter

281 Views
ybb34713
Contributor II

Hi Peter,

    I had the same problem as Max Lee ,but by studying the two routines you provided, but no configuration errors were found.Here is my code.I just need to get three ADC.

void CTU_Init(void)
{
    /* Enable input */
    CTU_0.TGSISR.R = 0x00000001; /*I1_RE*/

    /* Compare registers */
    CTU_0.TCR[0].R = 160;

    /* Counter */
    CTU_0.TGSCCR.R = 4000;
    CTU_0.TGSCRR.R = 0;
    CTU_0.TGSCR.R  = 0x0100;    /* Prescaler Value is 1 and Triggered Mode */
    /* Enable triggers */
    CTU_0.THCR1.R  = 0x00000061; /* Enable Triger 0 and set to ADC */

    /* Set ADC messages */
    CTU_0.CLR[0].A.R = 0x4000;/* Command 0 - last command in command sequence,sample ADC0-CH0, result to FIFO0 */
    CTU_0.CLR[1].A.R = 0x0002;/* Command 1 - first command in command sequence, sample ADC0-CH2, result to FIFO0 */
    CTU_0.CLR[2].A.R = 0x0007;/* Command 2 - next command in command sequence,sample ADC0-CH7, result to FIFO0 */
    CTU_0.CLR[3].A.R = 0x4000; /* stop the sequence, first command of second sequence which is not started */

    CTU_0.FTH.R = 0x00000002; /* set FIFO 0 threshold to 2, overflow is set when 3 results comes */
    CTU_0.FCR.R = 0x00000004; /* FIFO 0 threshold overflow interrupt enable */

    CTU_0.CR.R = 0x0003; /* General reload and TGS input selection reload */
}

void FUN_HW_CTU_FIFO0_INTC(void)
{
     uint32_t fifo_status;
    fifo_status = CTU_0.FST.R & 0xf;

    if (fifo_status == 4)    // if overflow
    {
        HW_AD_CRTA_u16 = (u16) (CTU_0.FR[0].R & 0xfff);//ADC_0.CDR[0].B.CDATA;
        HW_AD_CRTC_u16 = (u16) (CTU_0.FR[0].R & 0xfff);//ADC_0.CDR[2].B.CDATA
        HW_AD_CRTB_u16 = (u16) (CTU_0.FR[0].R & 0xfff);//ADC_0.CDR[7].B.CDATA;

        CTU_0.CR.B.GRE  = 1;    // CTU General Reload Enable
    }

    if (fifo_status == 8)    // if overrun
    {
    CTU_0.FST.R = 8;    // clear overrun flag
    }
    CTU_EFR = CTU_0.EFR.R;
}

0 Kudos

281 Views
maxlee
Contributor II

Hi Peter,

Thanks for your reply.

You are right. I found a minor mistake in my code and I've solved this problem. Everything work fine.

Max

0 Kudos

268 Views
mariuslucianand
NXP Employee
NXP Employee

Hello @maxlee ,

I know it's been two years since this post, but can you please detail the issue that caused this behaviour?

Regards,
Marius

0 Kudos