PCA21125 SPI problem

[supra0309]

Hi :

I'm using PCA21125 with SPI to do RTC function on 5746R. Here's my SDK setting(fig1/2, CS out1 in DSPI4). When I set command in "RTC_Cmd_Trans(0x92, 0)" to read time data from second(I haven't used "SPI_SetSS" to set CS1_4 = high). The initial SPI4 sout from MCU always be high, but it should be low which showd in PCA21125 spec.

How should I fix it? Or is there any sample code? thanks. 

BR,

Xantia

[PetrS]

Hi,

I understand initial level on SDO does not matter for this config and RTC device. With (CPOL=0, CPHA=0) config, once CS is asserted the SPI is placing first data bit on SOUT. After defined delay (tCSC, PCS to SCK delay) the master outputs the first edge of SCK and the master and slave devices use this edge to sample the first input data bit on their serial data input signals. At second SCK edge output data are changed. You should rather config SCK to PCS delay, PCS to SCK delay and delay between transfers for some reasonable values. DSPI_MasterSetDelay function can be used.

BR, Petr

[supra0309]

Hi :

So how should I set SDK to make sout of SPI4 to be initail low? Cause I try lots of associations, just can't make it(fig2).

BR, Xantia

[PetrS]

Hi,

if Fig22 shows SDI low before CS asserting, it does not mean it must be low. For device it is don't care, it is deselected For used SPI mode asserting CS both master and slave shift first bit on its output. So signals should be fine, just you should play little bit with delays, as I wrote.

BR, Petr