NAND Flash Boot Process Question

[Tim562]

Hi All,

I'm troubleshooting an intermittent boot problem on an MPC-5125 processor booting from a Micron NAND flash part. The processor manual states that the processor boot logic attempts to read the bootstrap utility from row address 0 at the start of the flash device (Block_0, Page_0, Column_0). At this address it does a burst read of 4 pages (about 4K of data). If no ECC failures, the boot read is considered successful and the process terminates. BUT, if an ECC failure is detected, the manual states that additional reads will be conducted at row address 256, 512 and 768. Here's my question, "what address is being referred to when the words "row address" are used?" My understanding of "row address" is that it represents the combined Column, page, block and LUN values. Since the bottom 16 bits of the full 5 byte row address represent the column address(byte within a page), is this implying 4K reads are made from columns 0, 256, 512 or 768 of the first page, block, LUN? If that's the case it's not very useful for redundancy since the 256 bytes between row addresses doesn't allow the storage of a complete bootstrap utility (remember 4k is read from each start address).

It would make more sense if the term "row address" referred to the starting block for a 4 page read. Can anybody help clarify this for me? Thanks in advance! ~Tim

Here's how the 5 byte flash address spec is divided up for the Micron flash part I'm using

        +--+----------> Bits[15-0] specify the column address (0-4319)

        |  |

0x0000000000

  ||||||

  ||||++--------------> Bits[22-16] Page address (0-127)

  ||||                  Bit [23] Plane select bit

  ||||

  ||++----------------> Bits[31-24] Block select bits

  ||

  ++------------------> Bits[34-32] Block select bits

                        Bit [35] LUN spec bit

[Pavel · Accepted solution]

The page address and the block address, collectively, constitute the row address.

The column address identifies the byte or word within a page to access.

See the following documents:

https://www.ece.umd.edu/~blj/CS-590.26/micron-tn2919.pdf

and

http://www2.lauterbach.com/pdf/nandflash.pdf

If an ECC failure is detected, additional reads will be conducted at row address 256, 512 and 768 (256, 512 and 768 pages).

Have a great day,
Pavel Chubakov

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[Tim562]

Thanks for your reply Pavel, would you happen to know if the MPC-5125 NFC power on reset logic uses the RB (ready/busy) signal from the NAND flash part to determine when it is ok to send the reset command (0xFF) to the flash and start the power up read of the bootloader code? The microcontroller reference manual (section 23, Nand Flash Controller) is pretty thin on details of how the boot process and timing works. It does mention sending the flash reset command and the 4 separate reads from 4 different flash locations, but that's about it.

Best,

Tim