Marking memory region non-cacheable for DMA

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Marking memory region non-cacheable for DMA

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mgssnrlwl
Contributor II

Someone took the original MPC5744 startup code (found in the example projects files in S32DS) and added a section to the memory map @ 0x40000000 (start of System RAM) and called it ".datanocache".  Then they put various data objects there.

However, I can't find any way that this data is NOT being cached.

It seems to me like this was a complete waste of time.  So far as I can tell, there's no way to (nor are there any instructions in any of the code that could) turn off data cache for a particular region.

If I'm correct, I can get rid of this useless confusing bit of nonsense.

If I'm incorrect, how would one go about disabling a region of RAM from being cached to be safely used with DMA?  Or is this SOC smart enough that its DMA and cache work together?

Thanks!

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petervlna
NXP TechSupport
NXP TechSupport

Hello,

The cache for certain region can be inhibited via MPU. For particular descriptor you will define range and then disable inhibit cache.

For more details please refer to core reference manual Chapter 10 Memory Protection Unit.

If I'm incorrect, how would one go about disabling a region of RAM from being cached to be safely used with DMA?

Exactly for this purpose there is cache inhibit. As this micro does not have cache coherency unit.

petervlna_0-1691564687359.png

Best regards,

Peter

 

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mgssnrlwl
Contributor II

So, I figured out where the disconnect was.

In the SMPU_Init() function, which was borrowed from one of the NXP S32DS sample projects for MPC57xx, the addresses of the non-cacheable and cacheable regions were hard coded, as opposed to using symbols from the linker file.

Once I remembered the SMPU code, I found what I was looking for pretty quickly, and made the function more generic by referring to the appropriate symbols in the linker file and programming SMPU_0.RGD[X] and SMPU_0.RGD[Y] with the appropriate start and end registers.  The CI and VLD bits in WORD3 were already programmed properly.

Incidentally, this information is covered in the PRM in chapter 20 on the SMPU.

Thanks all.

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petervlna
NXP TechSupport
NXP TechSupport

Hello,

The cache for certain region can be inhibited via MPU. For particular descriptor you will define range and then disable inhibit cache.

For more details please refer to core reference manual Chapter 10 Memory Protection Unit.

If I'm incorrect, how would one go about disabling a region of RAM from being cached to be safely used with DMA?

Exactly for this purpose there is cache inhibit. As this micro does not have cache coherency unit.

petervlna_0-1691564687359.png

Best regards,

Peter

 

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mgssnrlwl
Contributor II

Thank you, Peter.  I was looking in the wrong place.

I'll report back when I get my needs figured out.

Regards,

Matt

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