MPC5777M : interrupt hardware mode configuration

[paulodasilvapin]

Hello,

Until now, I've set up the INTC controller in software mode keeping the HVENx bits to 0.

At the same time, the IVPR register was pointing to an exception vector table (from critical exception vector to floating point round vector).

With this mode, I was able to get an external interrupt exception vector where I can identify the source of the interrupt (looking at the IACKR register of the INTC and acknoledge it with the EOIR register).. 

Now I'm trying to use the hardware mode (putting the necessary HVENx bits to 1). I've got a ISR table aligned to 256bytes and where each entry has a size of 4 bytes and I set the IVPR to the address of this table.

How do I inform the core to find the exceptions vector. With the 5566, we have used the mtivor instruction to set each ivor individually but how do we perform analog operation in the MPC5777M ?

Do you have please any piece of code and linker command file where can I found an implementation of the hardware mode ?

Best regards

Paulo

[davidtosenovjan]

As I know the only device from MPC57xx family using the same approach as MPC55xx (with IVOR registers) is MPC5777C. All others devices use fixes offsets (as it was on e200z0 core).

Here you may see example code:

Example MPC5744P HardwareVectoreMode S32DS 

Also I am attaching startup code from S32 compiler.

Maybe following discussion could be useful:

interrupt definition 

[paulodasilvapin]

Hello David,

I found the reason why the interrupt number was updated in INTVEC field of IACK register. The corresponding interrupt was an STM interrupt.

When debugging with Trace32, I need to set the option  SETUP.StepAllCores ON so that the freeze bit of the STM module works.

Best regards

Paulo

[paulodasilvapin]

Hello David and thank you for your quick answer.

With the provided example I was able to detect 2 différent interrupts in hardware mode. The offset of 0x1000 for the ISRs table was the difficult point for me. Where is this documented in the TRM ?

Another question : when an entry of the ISR table is reached because of an interrupt , I can see that the INTVEC field of the IACKR register is set to a value XX for example. But immediatly after I execute the branch then the field is updated to a value YY.

From the TRM, we can read :

"When the interrupt request to the associated processor asserts, the interrupt vector signal

is updated. The value of that interrupt vector is the unique vector associated with the

preempting peripheral or software-settable interrupt request. The vector value matches

the value of the INTVEC field in the INTC_IACKRn, depending on which processor was

assigned to handle a given interrupt source."

Then I thought that the INTVEC field is updated as it was in software mode.

Where am I wrong ?

Regards

Paulo