Hello,
I am seeking clarification on the numbering used for masters and slaves in XBIC_0 and XBIC_1 on the MPC5777M.
When attempting to inject an error on XBIC_0 during a write transfer from core 2 (the IOP core) to internal SRAM, I followed the XBAR port numbering and selected master 4 and slave 4. However, no error was detected—the write transfer completed normally. If I select master 2 instead — which seems unrelated to the expected data path — an error is detected.
I have observed similar behavior on XBIC_1: using master 4 does not result in the expected error detection, while selecting master 2 does.
Could anyone confirm the correct numbering for masters and slaves in XBIC_0 and XBIC_1? Are the XBIC and XBAR numberings different?
Thank you in advance!
