MPC5777M PLL configuration

[paulodasilvapin]

Hello,

Working on the PLL configuration, I have read in the MPC5777MRM.pdf on page 1206 that:

"The system clock dividers are synchronized to each other such that the rising edges of the

lower frequency clocks are aligned with those of the higher frequency clocks. This,

however, imposes limitations on the division factors which can be used. In order for the

synchronization to work properly, each division factor must be selected such that its

value is an integer multiple of each division factor that has a lower value"

On page 1208, it is given a correct example of configuration on table 29-4.

However, I don't understand why CGM_SC_DC0[DIV] is choosen with value 3 since it is not a integer value of CGM_SC_DC3[DIV] which has a value of 2.

Moreover, is the order of the configuration of these registers important ?

Paulo 

[PetrS]

Hi,

The MPC5777M supports a 3:2 ratio between Core clock (COMP/CHKR clock = 300 MHz) and Crossbar (fast XBAR clock = 200 MHz). So DC3 setting is correct, DC2/DC1 and DC0 should follow mentioned recommendations. You should also keep the order which is stated in Table 29-4.

BTW there is an app note dealing with CGM initialization, see http://cache.nxp.com/files/microcontrollers/doc/app_note/AN4812.pdf.

BR, Petr

[paulodasilvapin]

Another remark,

in the application note the field CLKCFG of

PLLDIG_PLL0CR/

PLLDIG_PLL1CR registers

 are written but this field is marked as ReadOnly in the TRM (page 1115). I'm using T32, and I see that theses registers have a value of 0x00000100 and I can't modify them. How can I set the CLKCFG field to normal mode ?

Paulo

[paulodasilvapin]

Thank you for your answer and the provided application note.

I have use the provided code and I have noticed that when the MC_CGM_DIV_UPD_TRIG register is written then the core registers r0 to r31 of the CPU_2 are modified to undefined values.

Did I miss something ?

Paulo