MPC5777C Optimization

[darq]

Hello,

I am trying to improve system performance (task execution times) but i am not sure what else could be optimized except the things mentioned in AN5191 Software Initialization and Optimization. Any suggestions would be greatly appreciated.

Best regards

[davidtosenovjan]

The appnote is quite accurate, I think.

You can

- lock time critical tasks into cache
- you may use eDMA to offload the cores
- use compiler optimization

One yet note to internal SRAM - there are two instances for two SRAM spaces (0x4000_0000-0x4003_FFFF and 0x4004_0000-0x4007_FFFF) accessed over two separate ports. Accesses are concurrent unless the both cores accesses over the same XBAR port. So this optimization would be in distributing data between both SRAM portions accordingly.

[darq]

Thank you for your reply.

What do you mean lock tasks into cache? How could i do that? Is there some documentation that i could read about it? At the moment instruction and data caches are enabled.

We use eDMA as much as possible specifically due to this reason.

We try to avoid compiler optimizations due to various articles describing what those optimizations can do and mistakes related to it.

The suggestion for distributing SRAM is nice. We will go for assigning one port for each core.

Any other suggestions?

[davidtosenovjan · Accepted solution]

I havent meant 'tasks' in the meaning of OS - just code portion, it you have some time critical assembly function or some NVM data for instance, you may lock it 1in cache, then it acts as additional RAM. The procedure you may find, example 9:
https://www.nxp.com/docs/en/application-note/AN2865.pdf

However I just relalized that according AN5191, it is recommend this way to lock stack in the cache memory. So it is up to you.