MPC5777C DSPI SCK vs. MPC5674F

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

MPC5777C DSPI SCK vs. MPC5674F

1,496 Views
ricardofranca
Contributor III

Hello,

I am replacing an MPC5674F (264MHz) with an MPC5777C (300MHz) in a project and I am a bit confused when trying to compute DSPI SCK for the new MCU.

 

- It seems DSPI SCK for the MPC5777C must be at most 30MHz and DSPI_CLK must be at most 100MHz. I did not quite understand what are these upper bounds for MPC5674F... does "t_SYS" means the same in both datasheets? The MPC5777C datasheet describes t_SYS as the period of DSPI_CLK, being at least 10ns/100MHz, but I could not understand the meaning of t_SYS in the MPC5674F datasheet. Is t_SYS the inverse of f_SYS (i.e. 1/264MHz) or the inverse of the peripheral clock (1/132MHz)?

- Why did the DSPI had such a significant maximum SCK decrease from the 5674F to the 5777C?

- Shall I use PER_CLK at 100MHz or lower if I intend to use DSPI?

- Is there any combination of clocks and multipliers for me to have DSPI SCK at 30MHz with core clock at 300MHz?

Thanks,

Ricardo

0 Kudos
Reply
3 Replies

1,477 Views
davidtosenovjan
NXP TechSupport
NXP TechSupport

MPC5674F:
tSCK = 1/fperiph
fperiph=fplatf

If SIU_SYSDIV[IPCLKDIV] = 0 (Enhanced mode): fcore=fsys, fplatf=fsys/2=fetpu
If SIU_SYSDIV[IPCLKDIV] = 1 (Full mode): fcore=fsys=fetpu, fplatf=fsys/2
If SIU_SYSDIV[IPCLKDIV] = 3 (Legacy): fcore=fsys=fplatf=fetpu

MPC5777C:

davidtosenovjan_0-1765389023674.png

davidtosenovjan_1-1765389034100.png

It can also be limited by used pad types, both devices are based on different nm technology.

 

0 Kudos
Reply

1,412 Views
ricardofranca
Contributor III

Hello David,

I did not understand the references to eTPU - for the moment, I am staying away from it and I could not see any relationship between it and the DSPI clocks. From the MPC5777C datasheet table 44

ricardofranca_0-1765554856751.png

 

It seems that maximum frequency of DSPI would be 30MHz. Also in this table, note 6 states that "tSYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min tSYS = 10 ns). " Thus, even if PER_CLK can reach 150MHz, it seems to me that I am bound to 100MHz if I use DSPI. Is that right?

 

 

0 Kudos
Reply

1,297 Views
davidtosenovjan
NXP TechSupport
NXP TechSupport

On MPC5777C fetpu only relates that in the fastest option is fperiph*2

davidtosenovjan_0-1765801282694.png

 

Maximum DSPI frequencies are explicitly mentioned below:

davidtosenovjan_1-1765801282699.png

 

100MHz is a limit, if you use clock calculator (AN12176), it is checking this parameter:

davidtosenovjan_2-1765801282707.png

 

 

0 Kudos
Reply