Dear NXP Professionals,
I have a problem about PIT timer and this problem is probably about clock config. Although I did debug with detail, I could not solve my problem and to put a help message here is only way for me anymore. Could you check my purpose and code whether ı am true or not. I am looking forward to hearing your responses.
My purposes type by type:
PLL0_PHI : 120 MHz
PLL0_PHI0 : 120 MHz
PerClk(CMU_5) = 60 MHz
My Code
// First of all, we did some setting in SYSDIV register. These settings are below type by type.
// 1.Progressive Clock Switch is set to 1.
// 2.System Clock Driver Division coming out of PLL1 is 1.
// 3.ETPU division is 2.
// 4.System clock is PLL0.
// 5.PLL0 is a clock source for MCAN module.
// 6.Divider is equal to 2 for CMU5(communication)
// 7.Divider is equal to 2 for CMU3(communication)
// 8.PLL0 is the clock source for eTPU and communication.
// 9.XOSC is the source for PLL1
// 10.XOSC is the source for PLL0
// 11.Register and all bits are accessible.
SIU->SYSDIV = 0x0100B01D;
// Secondly, we run the PLL0 in normal mode.
PLLDIG->PLL0CR = 0x300;
// rfdph0 is 4 - For PLL0-PH1, clock divider is equal 4.
// rfdph1 is 4 - To make PLLO-PH0 120 MHz.
// Pre-divider for PLL0 is equal to 2.
// MFD is 24 // it is calculated by looking at page 858 in order to edit PLLO-PH0
PLLDIG->PLL0DV = 0x10042018;
// to wait PLL0 is locked.
//
while (!(PLLDIG->PLL0SR |= ~(1 << 2)))
{
}
