MPC574xk LINFlexD UART receive 12 bit serial data.

[Birsen]

Hi NXP Community, 

I work with an SBC IC that comminicate with MSC (Micro Sec. Commun.) protocol.  MPC574 MCU wants to receive data from this SBC IC by using LINFlexD UART protocol. There is 16 bits frame size that has 1 start bit, 4 address bits, 8 data bits and 2 stop bits. Thus 12 bits UART data should be received from MCU. 

How I configure LINFlexD registers for this purpose?

[Birsen]

Dear Peter thank you for your response,

Actually, I read this document and WLS is set as 1, and WL1 AND WL0 are set as 1. However, in this configuration it does not work.

LINFlexD_14.LINCR1.R = 1;

LINFlexD_14.UARTCR.R = 1;

LINFlexD_14.UARTCR.B.WLS = 1; 

LINFlexD_14.UARTCR.B.SBUR = 1; 

LINFlexD_14.UARTCR.B.WL0 = 1; 

LINFlexD_14.UARTCR.B.WL1 = 1; 

LINFlexD_14.LINFBRR.R = (uint16_t)(div & 15U); /* Fractional divider. */
LINFlexD_14.LINIBRR.R = (uint16_t)(div >> 4); /* Integer divider. */

LINFlexD_14.UARTSR.R = 0xFFFF;

LINFlexD_14.UARTCR.B.RFBM = 1U;

LINFlexD_14.LINCR1.R = 0;

My configuration as above. However, it does not work. When WL0 is set 1 and WL1 is set 0, I can receive data, but these data are missing and confusing. 

[PetrS]

Hi,

does that mean no flags are set in UARTSR (RDF or errors) for incoming frame?
Can you show frame received using scope/analyzer?
RxEn bit is not set, but probably you did it later.

BR, Petr

[Birsen]

Actually, I can see message in both situation on logic analyser. And these signals are correct.

However, I can not receive data in DMA Buffer. When WL0 =1 and WL1 = 1 are set as 1, DMA Buffer is empty. When WL0 = 1, WL1 =0 are set DMA buffer is not empty, but receive data is missing or complex. (Not: RxEn bit is set) WL0 = 1, WL1 = 1, WLS = 1, SBUR =1WL0 = 1, WL1 = 1, WLS = 1, SBUR =1WL0 = 1, WL1 = 0 WLS = 1, SBUR =1WL0 = 1, WL1 = 1, WLS = 1, SBUR =1

[Birsen]

Moreover, I set the receiver buffer length as 4. The entire image of the receiver buffer is as follow image.

[PetrS]

Hi,

I assume module should be set for 13bit frame 

BR, Petr