MPC5748G Weird SPI behavior with PCSIS

darq

Hello,

I have observed a weird behavior of SPI interface on MPC5748G micro-controller. When the PCSIS field in MCR register is set to 0x3F (all bit set meaning all CS active low) the behavior is as expected. Example is shown on the picture below. Signals are:

yellow - clk

pink - miso

blue - mosi

green - cs

When the PCSIS is set only for a specific CS like 0x01 (only first CS active low), then the behavior is as on the picture below. The miso signal have at least four different signal levels and is driven even outside of clock signals.

Could anyone help me understand this? There is no difference in the code and setup except for changing of setting PCSIS in MCR register.

Any help would be greatly appreciated.

Best regards

PetrS

Hi,

what is your connection in fact? Do you use other PCSs as well to control more slaves? I assume MPC5748G is a master here, or not?
If more slaves are connected then this setting can cause more slaves will drive its output, if SPI will set inactive state low for more PCSs.

BR, Petr

darq

Hello,

Thank you for your response.

In this specific case only one CS is used, MPC5748G is a master and there are no other chips connected to this SPI interface but for some reason MISO behaves correctly only in case 0x3F is written to PCSIS in MCR register.

I have also tested on a different board with MPC5777C where all CS are used in DSPI interface and when one of the CS is excluded in PCSIS it also behaves incorrectly.

Best regards

PetrS

Hi,

unfortunately I am not aware of wrong SPI operation and I have not met with such behavior in past. Can you share your SPI and pin configuration and a code used for this frame. Also share your connection/schematic for connected device.
MISO is driven by connected device and with the only one it would work. Anyway you can double check below...
- master and and slave are using same supply voltage ranges. Be sure ground is properly connected between.
- try to enable weak pull-up for SIN pin

BR, Petr