MPC5748G ESW peripheral congested

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MPC5748G ESW peripheral congested

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Daniel_Wax
NXP Employee
NXP Employee

Seeing an issue with the ESW where port 0 seems to become congested, and then no traffic is let through. (see attached screenshot)

 

It seems very intermittent as I see it occur every 3rd boot cycle on the microprocessor, and it seems to do with the order of initialization of the ESW and ENET. The bandwidth of traffic on this network is not high at all.

 

Is there anything I should be careful about during the initialization sequence of the ESW and ENET0/1 peripherals? The thing that’s new is setting the DUCR.UP0/1/2 bits in the ESW as well as turning off promiscuous mode on the ENETs and initializing the IAUR/IALR unicast MAC address hash table.

 

Let me know if other information would be helpful.

 

 

Daniel_Wax_0-1661213160423.png

@scottobrien 

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lukaszadrapa
NXP TechSupport
NXP TechSupport

Hi Daniel,

I created new case 00485086 on your behalf for AE team...

Regards,

Lukas

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