MPC5748G CAN

[徐工2024]

Hello, I would like to ask some questions about can0 receiving interrupt, I implemented is to receive all can id messages:
Question 1: My program does not know why it can only enter the interrupt if MB[5] interrupt is enabled, and why reading MB[0] can read the correct message at this time. If I enable MB[0] interrupt, I cannot enter the receive interrupt, why? I read the message content of MB[0] and should also enter the MB[0] interrupt, here is my code.

[徐工2024]

Thank you for your reply. Yes, I enabled RX FIFO, but I still have the following problems:
Question 1: According to the manual, if RX FIFO is enabled, MB[0~5] is occupied by RX FIFO (and I did not set the RFFN bit), but why MB[5] can enter the interrupt when sending data to CAN?MB[5] Isn't it occupied? Is there some kind of drinking relationship here?
Question 2: I don't quite understand the meaning of the RFFN figure, can you answer it for me?

Question 3: Why does this project need to read MB[0] of data after using MB[5] to enter the interrupt? Data projects that read MB[5] will go wrong, why?
Looking forward to your reply!
This is my project source code.Thank you！

[PetrS · Accepted solution]

Hi,

A1) as I wrote MB flags change meaning when RXFIFO is used.

So if there is new message in RXFIFO MB5 flag is set, if corresponding IMASK1 bit is set, interrupt is generated.

2) RFFN specifies how many filter elements will be used in RXFIFO. This will determine which MBs will be used by RXFIFO engine and ID Filter table, which MBs remains to be used for general TX or RX operation. Also specified how many filter elements will use individual masking registers, rest will FIFO global mask register. 

3) the CPU can read the message from RXFIFO by accessing the output of the FIFO  (MB0) as a Message Buffer and the CAN_RXFIR register and then clear the interrupt (MB5 flag). If there are more messages in the FIFO the act of clearing the interrupt (MB5 flag) updates the output of the FIFO with the next message and update the CAN_RXFIR with the attributes of that message, reissuing the interrupt to the CPU. Otherwise, the flag remains negated.

BR, Petr

[PetrS]

Hi,

your code only shows you enabled interrupt for MB[4] (IMASK1=0x10). It does not indicate, how MBs are configured and used. Commented code  and last MCR writing indicates RXFIFO is enabled. When RFEN is set, MBs 0 to 5 cannot be used for normal reception and transmission because the corresponding memory region (0x80-0xDC) is used by the FIFO engine as well as additional MBs (up to 32, depending on CAN_CTRL2[RFFN] setting) which are used as Rx FIFO ID Filter Table elements.
Low mask bits in IMASK1 also change its meaning, see more in 44.5.8 Rx FIFO chapter of the device RM.

BR, Petr

[徐工2024]

Sorry, there is an error in the project. The if judgment in can0_isr should be CAN0