MPC5748G CAN-FD sampling point

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MPC5748G CAN-FD sampling point

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704706705
Contributor I

Hi,

I have to configure sampling point in CAN FD as below.

■ sampling point

   - Arbitration phase : bitrate 1000kbit/s , 87.5% sampling point

   - Data phase : bitrate 5Mbit/s , 87.5% sampling point

■ MCU : MPC5748G(176pin)

My steps:

1. First select the clock source

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   so the maximum PE clock is 40MHZ.

pastedImage_6.png

2. calculate

Data phase calculation formula:

                     Sample point = (propagation segment + Phase segment1 +2)/(propagation segment + Phase segment1 + Phase segment2 + 3)

                     Bitrate =  PE Clock /((propagation segment + Phase segment1 + Phase segment2 + 3)*(Prescaler Division + 1))

              The known conditions:    PE Clock = 40Mhz ,  Bitrate = 5Mbit/s ,  Sample point = 0.875

      The results:            

pastedImage_13.png

The problem:

               1.Does MPC5748G support my configuration?

               2.Is the official recommended baud rate and sample point configuration table available?(Because the configuration value calculated by oneself can result in the lose data,   For example: Data phase :2.5Mbit/s  87.5%Sample point  will lose  of data

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1 解答
4,811 次查看
PetrS
NXP TechSupport
NXP TechSupport

Hi,

87.5% sample point in data phase cannot be achieved for 5MBit/s. With 40MHz PE clock NBT is 8tq long and min PSEG2 value is 2, this gives 75%.

However for this bit rate secondary sample point must be used as bit period is shorter that transceiver propagation delay -> you must get bit errors in data phase. So the TDC should be enabled and properly set. Use 1st PE setting and add following function in a code

FLEXCAN_DRV_SetTDCOffset(instance, true, 4);   // 4 is TDC offset, can be adjusted to get reliable communication.

For a bit timing calculation you can use this tool https://community.nxp.com/docs/DOC-342618 

BR, Petr

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4,812 次查看
PetrS
NXP TechSupport
NXP TechSupport

Hi,

87.5% sample point in data phase cannot be achieved for 5MBit/s. With 40MHz PE clock NBT is 8tq long and min PSEG2 value is 2, this gives 75%.

However for this bit rate secondary sample point must be used as bit period is shorter that transceiver propagation delay -> you must get bit errors in data phase. So the TDC should be enabled and properly set. Use 1st PE setting and add following function in a code

FLEXCAN_DRV_SetTDCOffset(instance, true, 4);   // 4 is TDC offset, can be adjusted to get reliable communication.

For a bit timing calculation you can use this tool https://community.nxp.com/docs/DOC-342618 

BR, Petr