Hi, in the AN4670 document and also in the generated startup.S code in S32DS it states that to disable the SWT the SWT_CR field should be set to 0xFF00010A, but according to the ref. manual the "A" would write on a reserved bit. Is bit 28 reserved or not?
Also only SWT1 should be enabled by default but when looking at the memory on position 0xFC050000 (SWT0) it reads 0xFF00011B, why is that?
Another issue/question is that in the generated startup.S (from S32DS) there is code to disable the SWT1 also for core 0....
A bit off topic ... but...I noticed that the crt0_core1_flash.s in AN4670 does not init the registers in the same order as in the startup.S....which of the two is the preferred way of doing it?
Finally I also have a problem with IVOR1 when writing to the registers....does anyone have a working example on how/when to enable the SWT? (I have already looked at Example-MPC5744P-SWT-Short-reset-v1_1-GHS614 without any success....)
This is quite simple. Just write in SWT WEN bit on watchdog you want to disable. You have to unlock CR register before write.
Always stick with RM and not with some S32DS examples. Reserved bit must be leaved untouched or it can lead to unpredictable behavior.
You can control from any core any SWT.
This Example-MPC5744P-SWT-Short-reset-v1_1-GHS614 is working correctly. Just have in mind that debugger by default disables SWT and you have to enable it in debugger if you want to debug this example!