I am using all 4 SPI busses on the Chip, and found the following. If I use an SPI with DMA in master mode I have no issues with it and it is working all the time. If I use an SPI in master mode with interrupts I found that if there is another SPI also using interrupts on a different bus transmitting at the same time the SPI set with the lower interrupt priority falls over. The received data on that SPI received by another device have CRC errors, and the data is not received all the time. The reason for using an SPI with interrupts is that it takes too much time to set up the particular SPI with DMA, I can not do this automatically with DMA via periodic triggering as the buffer and buffer size it transmits from varies all the time and is dependent on other things in the software. If I change the interrupt priorities around, the SPI with the highest interrupt priority always works, and the one with the lower priority always fails. I then shortened the message length and increased the clocking rate of 1 SPI to ensure that the transmit time of 2 SPI's on different busses using interrupts never overlap. So in other words when I start another SPI transfer on a different SPI bus with interrupts, there is no SPI that is configured with interrupts transmitting at that time. This solved my problem, but I would like to confirm if this is the case? If you want to have more than 1 SPI transmissions active at the same time at least 1 of them must be configured to use DMA? If you want to transmit 3 SPI transmissions on 3 different SPI busses at the same time at least 2 of them must be configured with DMA? Can you please confirm if my conclusion is correct?
Could you provide more details about CRC errors? I'am asking this because if you have multiple spi buses the worst case which should happens is an RX overflow, transmitted data to slave device shouldn't be affected.
All the SPI busses are running in Master Mode. When I was debugging on the Slave I could see that some of the data is repeated in the message I am sending from the Master to the Slave. For a test I was sending data that increments from 1 to the message size. In the message received by the slave some of the bytes was repeated. When I made the particular SPI interrupts the highest priority (TxFifo_IRQn) and (RxFifoDrain) the data received by the slave device ws correct.
I do SPI transfer in a timer interrupt routine. If I set the interrupt priority of the SPI higher than the priority of the timer interrupt, the SPI transfer works. If the priority is lower, the SPI Tx complete interrupt never triggers and if I read the status of the SPI it is in the failed state. The micro is running close to 100% processing capacity and if the SPI interrupt priority is too low there are other interrupts happening all the time before the SPI Tx complete interrupt could occur. The root of the problem is processing capacity, I have another question on that that I will ask in another post.