MPC5645: LPM_ACK asserting time by CPU for CAN modules

[Ramesh_A]

When the CAN modules are disabling by asserting the MDIS of the MCR, with that the modules are to be entered Low Power Mode. To confirm that the LPM_ACK will be set to TRUE by the CPU.

Want to know how many clock cycles are might be taken by the CPU to assert the LPM_ACK of MCR?

MPC564xB-C 

[petervlna]

Hello,

When disabled, the module requests to disable the clocks to the CAN Protocol Interface and Message Buffer Management sub-modules.

Want to know how many clock cycles are might be taken by the CPU to assert the LPM_ACK of MCR?

To set LPM_ACK it is just one clock cycle. I expect that LPM_ACK bit is acknowledge signal directly rooted from CAN module, so it will be one cycle. (as it is for other ACK bits of the other IPs). There is no need for delays, as it is not going trough any bus interface.

But if you are asking how many clock cycles will take from MDIS until the LPM_ACK is set, then:

If the module is disabled during transmission or reception, FlexCAN does the following:
• Waits to be in either Idle or Bus Off state, or else waits for the third bit of Intermission and then checks it to be recessive
• Waits for all internal activities like arbitration, matching, move-in and move-out to finish
• Ignores its Rx input pin and drives its Tx pin as recessive
• Shuts down the clocks to the CPI and MBM sub-modules
• Sets the NOT_RDY and LPM_ACK bits in MCR

Best regards,

Peter

[Ramesh_A]

Hi Peter,
Thanks for the information.
I've a question from one of the above points.
https://community.nxp.com/t5/MPC5xxx/MPC5645-LPM-ACK-asserting-time-by-CPU-for-CAN-modules/m-p/23409...
Can we consider that the bus goes idle when the inter-fame space (3bit-Recessive) is observed on the bus in case of Transmission/Reception of any TP message? and the CPU can consider this situation and set the LPM_ACK bit, so that the CAN modules entered Low Power Mode?