MPC5644A DSPI CSSCK behaviour

[kaifalkenberg]

Hello,

I have a question regarding the DSPI controller in the MPC5644A. I would like to configure a delay between the assertion of the chipselect and the first edge of SCK. When changing CSSCK[0:3] to something >0 I do indeed see a delay between the assertion of PCS and the first edge of SCK. But the same delay is now also present between each 8bit frame! Same goes for ASC[0:3].

Any ideas on what I might be missing? Or is this intended behaviour?

Thanks for your support

[davidtosenovjan]

Yes, it is correct behavior, all these times are supposed to be there. The only time disappearing between frames in case continuous transfer, it is tDT.

[kaifalkenberg]

From the RM, chapter 30.9.5.2:

"The PCS to SCK delay is the length of time from assertion of the PCS signal to the first SCK edge."

CS is asserted the entire time..

[davidtosenovjan · Accepted solution]

tCSC will be the always as you can see on the screenshot below:

[kaifalkenberg]

bump

[kaifalkenberg]

  Here are two screenshots illustrating the issue. Between both screenshots only CSSCK has been changed.