MPC5643L external clock source

[stefanodimasci1]

Hello,

I'm using the external clock source on the MPC5643L. THe problem is that I've found that the timers (e.g. PIT) expires as twice as slow than predicted. I think the clock I'm providing from the outside is divided from the internal plls, even if in ME_RUNX_MC I selected as SYSCLK the 4- 40 MHz oscillator instead of FMPLL. What register do I have to check? I'm sure that the system is using the external clock as the timeouts changes according to the external clock period.

Thank you very much.

[PetrS]

Hi,

The PIT is clocked from the Peripheral set 0 clock derived from the system clock which is divided by System clock divider 0. See Figure 10-1 of the device Reference manual. So if this divider is set to div by 1 (default value of CGM_SC_DC0 register) then the PIT is clocked from system clock. If you select ext osc (or ext clock) as system clock then PIT cannot run slowly, unless crystal and ext clock have different frequency. Similarly if PLL is used as system clock, it does not matter.

BR, Petr