MPC560xB DSPI utilization

[romainbenet]

Hey,

I use the DSPI 0 on MPC560xB (it's the same for the x=4 or 6) but I have problems. I use CodeWarrior 10.6

First part:

DSPI configuration: disable TX and RX fifos and overwrite authorized (field ROOE of MCR). CPHA = 0. SPI data size = 16 bits. DSPI_0 in master mode.

When I compile it I should write bit to bit for disabling RX and TX fifos (DSPI_0.MCR.B.DIS_RXF = 1 then DSPI_0.MCR.B.DIS_TXF = 1)

else fifos are again available when I write DSPI_0.MCR.R = 0x813F3001. Why?

And for the ROOE option of MCR register my debugger indicates that ROOE = 1 means incoming data is ignored (no overwritte).

What is the good definition of ROOE (datasheet or debugger)?

Second part: reading incoming data from SPI bus

I send by example 2 datas on SPI bus then I send another data for reading input data:

/** Send 0xFF00 to CS0 and CS0 still asserted after transaction */

DSPI_0.PUSHR.R = 0x8001FF00;

while (DSPI_0.SR.B.TCF == 0) {}

DSPI_0.SR.B.TCF = 1;

/** Send 0xF0F0 to CS0 and CS0 still asserted after transaction */

DSPI_0.PUSHR.R = 0x80010F0F;

while (DSPI_0.SR.B.TCF == 0) {}

DSPI_0.SR.B.TCF = 1;

/** Now I send a dummy command for reading SPI slave */

/** Clear previous data receiving */

u16DataRead = DSPI_0.POPR.R;

DSPI_0.SR.B.RFDF = 1;

/** Send dummy order to CS0  - last transaction of the command of 3 transactions */

DSPI_0.PUSHR.R = 0x000155AA;

while(DSPI_0.SR.B.RFDF == 0) {}

/** We receive data */

u16DataRead = DSPI.POPR.R;

DSPI_0.SR.R = 0x80020000;

/****/

For checking that my code is right I connect the S_OUT to S_IN of DSPI_0: input data = output data.

When I send data no problem (S_OUT).

My problems: the MPC560xB doesn't clear flags at DSPI_0.SR.R = 0x8002000 instruction: I have to clear bit to bit (TCF then RFDF fields of SR register). Why?

                       and the incoming data u16DataRead equals to 0x0F0F = previous sending and not 0x55AA. Why?

What is the good pratice for reading SPI input data when fifos are disables (like in my example).

Best regards,

Romain BENET

[PetrS]

Hi,

DIS_TXF and DIS_RXF cannot be set in the same time MDIS is cleared. So first enable module (MDIS=0) then you can set both DIS_TXF and DIS_RXF bits.

The RM is right with ROOE definition.

If the FIFO is disabled the DSPI operates as a double-buffered simplified SPI, so for receiving it is one entry in RX FIFO and one in shift register. So you are able to receive two frames without reading the POP register. Then if another data is received it is either ignored (ROOE=0) or put into a shift register (ROOE=1).

If RX FIFO is disabled, the best approach is to read the POP register each time the RFDF is set. You did not do it in your code, that’s why you read older data. Try to debug the code carefully.

The RFDF is not cleared as you have still unread data in “RX FIFO”

Note: to clear the w1c flags you should use the register access, the reason is well described in EB758 document; http://cache.freescale.com/files/32bit/doc/eng_bulletin/EB758.pdf.

BR, Petr