MPC5606B : EMIOS under Output Pulse Width and Frequency Modulation Buffered Mode

[raghavendrapura]

Dear Freescale Representative,

In  our application we are configuring EMIOS to work under Output Pulse Width and Frequency Modulation Buffered Mode for generating PWM with varied frequency and duty cycle.

I wanted to know what is the maximum frequency i could get with EMIOS pheripheral clock frequency set 64Mhz and Emios pre-scalar divide ratio 2?

How could i achieve a lager frequency range with EMIOS ?

Regards,

Raghavendra P

[PetrS]

Hi,

The CBDR should be written with a value greater then 1, counter is 16bit so max CBDR value is 0xFFFF.

The CADR can be any value. The CADR=0 produces 0% duty cycle, the CADR>=CBDR produces 100% duty cycle.

The PWM period is given by Temios_clk * (GPRE+1) * (UCPRE+1) * CBDR.

The min PWM period is generated with CADR=1 and CBDR=2.

For higher output rates you should select maximum slew rate for pad’s PCR register.

BR,

Petr

[raghavendrapura]

Hello Petr,

Many thanks for the information.

For our project we need frequency max range of 10Khz i.e 0.1 ms.

Could you please let me know the EMIOS_MCR register settings for a system clock of 64Mhz. [ GPRE value]

And also please tell us on the slew rate configuration for PAD. What should be the value to achieve above range.

I am using Rappid tool for pad configuration.

Regards,

Raghavendra P

[PetrS]

Hi,

There can be many setting, as you can see in the formula above. For example if I want to have channel clock equal to 1MHz, then for 64MHz system clock use GPRE=63.

To generate 10kHz PWM signal in OPWFMB mode use e.g. UCPRE=0 and CBDR=100.

There should be no issue with the signal edges on the 10kHz signal thus slew rate option does not make effect on it, I think.

BR, Petr

[raghavendrapura]

Hello Petr,

Many thanks for the information. Could you please let me know how i could stop the generating of PWM once it has been started.

Because in my application i am using PWM to control a Motor and once i reached a desired point then i need to stop the PWM.

Does a CADR count of 0 stops the pulses?

Regards,

Raghavendra P

[PetrS]

Hi,

You can stop the PWM counter by disabling the channel prescaler, using UCPREN bit.

Setting of CADR=0 generates 0% duty cycle in next PWM cycle.

The FORCMA and FORCMB bits allow the software to force the output flip-flop to the level corresponding to a match on comparators A or B respectively.

BR, Petr

[romainbenet]

Hi Petr,

for my application I need to halt the PWFMB (Pulse With Modulation and Frequency Modulation) at any time (the output state will remain the same) so I stop the clock of this channel (EMIOSC.bit.UCPREN = 0).

The register EMIOSCNT (internal counter) associated to this PWM can't be written in PWM mode.

But I have to reset the internal counter EMIOSCNT because I need to restart later properly with a new frequency and a new duty-cycle.

What is the good practice to reset (force EMIOSCNT to value 0) when I runs EMIOS in PWM mode?

Best regards,

Romain

[PetrS]

Hi,

Go through the eMIOS GPIO mode. Once you put eMIOS channel into GPIO mode internal counter is writable, so you can set it to 1. Then you can put the channel back to OPWFMB mode.

BR, Petr

[romainbenet]

Hi,

thanks you for your help.

Best regards,

Romain