MPC5604E Clock Architecture Issues

[suhass]

Hi,

I'm working on MPC5604E, and wanted to get clock out of "clk_out" pin [PCR36, Pin No. 62], according to Clock Architecture Block diagram [Refer "Img1"], Input to the "clk_out" pad is from FMPLL_0 after FMPLL_CLK_DIV, But according to over experimentation its not the case, according to what I have validated the input to "clk_out" is from FMPLL_0 before FMPLL_CLK_DIV. It also says maximum frequency supported on "clk_out" pad is 32MHz [Refer Img2]

but we have tested it upto 120MHz. Do clarify the issues.

Thanks & Regards 

SUHAS S

[lukaszadrapa]

Hi,

I have confirmed the same behavior on my board. Yes, the input for clk_out is before the divider. Thanks for pointing this out, I will report it.

Yes, it is possible that the clk out can be set to higher frequencies but we do not guarantee the functionality of the device in this case. It's out of our specification.

Regards,

Lukas