MPC5602B: Timing information needed on setting EHV-bit in FLASH_MCR

[franzhuber]

Hi all,

one urgent question about delay/stall of program-execution on first time setting the EHV-bit to initiate erase/write of flash.

Following setup of the hardware:

- External watchdog with fixed cycle-time of 200ms (can't be changed)

Now, on setting the EHV-bit it looks like the processor is going into a "stall" for longer than 200ms leading to a reset by the watchdog.

Has anybody else experienced this behaviour and maybe a workaround for this?

Kind regards

Franz

[lukaszadrapa]

Updating this old thread to provide the informaiton also to other customers:

Flahs on MPC5602B is composed of single bank. Read-While-Write is not supported. The code must be executed from RAM.

The response for read-while-write is programmable - there's also suport for stall-while-write. So, described problem is caused by code executed from flash while the response is set to stall-while-write.

Solution is to execute the code from RAM. The EHV bit is set immediately, there's no any delay.