MPC5554 EBI QUESTION

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MPC5554 EBI QUESTION

11,890件の閲覧回数
KAIH1
Contributor II

Hello, I have a long-standing question:
When I was testing the EBI bus on the MPC5554 development board, I configured it to 16 bit bus mode. When I forcibly changed the high and low level states from DATA0 to DATA15, I could see the changes in memory data at address 0x20000000 in online simulation mode, so I thought the bus was already connected. But when I officially used it, not in simulation mode, and changed the high and low level states from DATA0 to DATA15, there was no change when reading 0x20000000 memory data. What is the difference between these two modes (online simulation or not) that I cannot find?
Is it necessary to perform additional operations when updating the high and low level states from DATA0 to DATA15 to 0x20000000 memory in non simulation mode?
I hope any engineer can provide some advice.

MPC5554VBBOARDS 

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davidtosenovjan
NXP TechSupport
NXP TechSupport

Could you specify what you mean by simulation mode and non simulation mode? Do you mean running with debugger / without debugger?

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KAIH1
Contributor II

Hello, I also found a strange phenomenon during debugging. When a 16 bit bus read exception occurs, the value of the 0x2000000 memory area is copied to the value of the address 0x0000000, as shown in the figure below. I don't know what triggered the memory copy, and since I don't have an expanded memory area, I haven't performed a memory copy operation. Where should I configure to disable this copy operation so that it does not affect my address 0x20000000 bus data reading.

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davidtosenovjan
NXP TechSupport
NXP TechSupport

Apparently device is configured to external boot mode. It configures MMU in order to boot from address 0x0. It is what you see like copying.

davidtosenovjan_0-1728486158643.png

 

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KAIH1
Contributor II

Thanks for your reply, I feel close to the truth. But as you can see in the figure below, my hardware is indeed configured for internal memory boot, not external memory boot. I still don't know where the problem is causing the program to start from the outside.

KAIH1_0-1728533040040.png

 

KAIH1_1-1728533071684.png

 

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davidtosenovjan
NXP TechSupport
NXP TechSupport

Then the device is in serial boot mode because of no valid RCHW has been found

davidtosenovjan_0-1728556420074.png

davidtosenovjan_1-1728556571810.png

 

 

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KAIH1
Contributor II

Hello, the issue seems to be stuck again, and I have to suspect that it may be an evaluation version of my CodeWarrior software that is causing my EBI bus to be unusable. Please help me confirm again.

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davidtosenovjan
NXP TechSupport
NXP TechSupport

It is otherwise. By default MMU is setup as follows.

davidtosenovjan_0-1728978112361.png

RM has it stated incorrectly. But some others from the MPC5500 has is right, for instance MPC5566.

davidtosenovjan_2-1728978238583.png

With this setup, both addresses 0x0000_0000 and 0x2000_0000 reads physical address 0x0.

You need to re-configure entry 2 to have logical and physical addresses both at 0x2000_0000.

 

 

 

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KAIH1
Contributor II

Thank you for your feedback. I found an example of MPC5777 before and tried to configure my MPC5554, but some instructions were different (such as instruction e_lis e_or2i、se_bgeni、e_ori、se_isync), I didn't try successfully. The function is as follows. Can you help me make some rough modifications? Thank you.
static asm void External_SRAM_MMU_init(void)
{

e_lis r3,0x1006 // Select TLB entry#, define R/W replacment control
mtspr MAS0,r3 // Load MAS0 with 0x1002_0000 for TLB entry #2

e_lis r3,0xc000 // setup 512MBytes to cover the whole EBI space
e_or2i r3,0x0980 // TLB valid, protected from invalidation
mtspr MAS1,r3 // Load MAS1 with 0xC000_0980 for TLB entry #2

se_bgeni r3,2 // virtual address at 0x2000_0000
e_ori r3,r3,0x0038 // VLE, cache-inhibited, write through
mtspr MAS2,r3 // Load MAS2 with 0x2000_0038 for TLB entry #2

se_bgeni r3,2 // physical address at 0x2000_0000
e_ori r3,r3,0x003f // all accesses permitted
mtspr MAS3,r3


msync // make sure we finished all memory accesses
tlbwe // Write entry defined in MAS0 (entry #2 here) to MMU TLB
se_isync // Wait for tlbwe to complete, then flush instruction buffer
}

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davidtosenovjan
NXP TechSupport
NXP TechSupport

All these code is already done in INIT_ExternalBusAndMemory in attached file taken from basic blank project.

MPC5554 use BookE code whilst MPC5777C VLE code usually.

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KAIH1
Contributor II

Thanks again for the reply, but in the program, I have indeed defined RCHW, as shown below, and looking at the memory 0x0000 address space, 5A keyword has been successfully written. What else could be the reason? I really can't find the problem.

KAIH1_0-1728625739368.png

KAIH1_1-1728625968501.png

 

 

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KAIH1
Contributor II
Thank you for your feedback.
Yes, when there is no debugger, I send the data through SCI
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11,833件の閲覧回数
davidtosenovjan
NXP TechSupport
NXP TechSupport

If application works correctly in debug mode, but not standalone, usually it is because of debugger script executes certain configuration that is missing (for instance watchdod disabling or MMU configuration or so).

Another point is whether you see issues when you let the code frrely run in debug mode, or you need to step it to get correct results.

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KAIH1
Contributor II
Thank you again for your feedback:
1. However, I would like to know if the debugger script is configured correctly (regarding EBI) and if a correct example can be provided;
2.In debugging mode, there are no issues and the results are completely correct;
3. Regarding EBI, I would like to know its operating principle, how data reaches the 0x20000000 memory area when it reaches the DATA0 to DATA15 data line, and whether additional external pin inputs such as TA pin or CS/RD are needed
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