I finally found the problem causing problems on our own boards.
It has to do with the TEST_SEL_1 pin which requires a pulldown resistor.
On our board, I blindly followed the Lite5200B eval board and used a 10k pulldown. The problem is that I also have an FPGA connected to the LP bus. The TEST_SEL_1 pin doubles as the TSIZ2 (transfer size) for non muxed mode of LP bus so this pin is routed to FPGA IO on our board.
The FPGA has weak pullups on its IO that are always active before configuration. The combination of the weak pullup and and 10K pull down put the TEST_SEL_1 pin just below its switching threshold. Low temperatures were enough to lower the temperature dependent FPGA pullups to the point of this pin going high during board reset.
Lowering the value of the pulldown to 1k fixed the problem.