MPC5121 conjunction with SGTL5000 I2S codec

[Breeze]

Hi,

I try to use MPC5121 PSC5 as I2S to conjunction with SGTL5000.

PSC5_4 defines as MCLK, my problem is no MLCK output at IO pin PSC5_4 after my register setting entry.

Here are the setting content in uboot mode,

mw 8000a270 0		;PSC5_0 in FUNCMUX
mw 8000a274 0		;PSC5_1 in FUNCMUX
mw 8000a278 0		;PSC5_2 in FUNCMUX
mw 8000a27c 0		;PSC5_3 in FUNCMUX
mw 8000a280 0		;PSC5_4 in FUNCMUX
mw 80000f04 e140bc00	;SCCR1 (System clock control reg.1)	PSC5 enable
mw 80000f08 bc800000	;SCCR2 (System clock control reg.2)	I2C0 enable (SGTL5000 control thru I2C0

mw 80000f30 00300000	;P5CCR (PSC5 Clock Control Reg.)	set MCLK_DIV=24	SGTL5000 accept 8-27MHz
mw 80000f30 00310000	;P5CCR (PSC5 Clock Control Reg.)	enable MCLK, MCLK=SYS_CLK/25	SGTL5000 accept 8-27MHz

mw 80011540 2fe00000

;SICR (Serial Interface Control Reg.)

Can any expert help reply?

Thanks in advance.

Gilbert

[genuap]

I'm not an expert on this part, but looking at the documentation, have you gone through this document:

http://cache.freescale.com/files/microcontrollers/doc/user_guide/MPC5121EQRUG.pdf?fpsp=1

Section 4.4. goes through a 7 step process to get MCLK_OUT to output.