LMLR and SLMLR reset configuration

[jeffcampbell]

What exactly is controlled by, for example, FLASH_B_LMLR and FLASH_B_SLMLR reset configurations in Shadow Block B?  The reference manual says they control the reset state of the LMLR and SLMLR for Flash B, which makes sense.

But, I've tried altering the values to allow the chip to reset with some blocks of memory unlocked, and have had no luck.  I can confirm that the reset configuration words in the shadow block are being properly modified but the LMLR and SLMLR are resetting to different values.  Does something else have an impact on their reset states?

Edit - I modified the LMLR and SLMLR reset words in shadow block A, and saw the corresponding changes take place in the LMLR and SLMLR for flash A upon reset.  So the problem only seems to occur with Flash B.

[jeffcampbell]

Figured it out. According to the MPC5674F reference manual Rev 7, these are the following addresses for the LMLR and SLMLR (Flash B) reset configuration words:

LMLR: 0x00EFDDE8

SLMLR: 0x00EFDDE8

But it turns out they're actually shifted versions of the LMLR and SLMLR reset words for Flash A:

Flash A values:

LMLR: 0x00FFFDE8

SLMLR: 0x00FFFDF8

Flash B values:

LMLR: 0x00EFFDE8

SLMLR: 0x00EFFDF8

Modifying THESE addresses brought the right changes in the LMLR and SLMLR for Flash B.  So I guess this is just a typo in the manual.

[lukaszadrapa]

Hi,

thanks for sharing this. Yes, your observation is correct, it's a typo in the reference manual. I will create a ticket for documentation team to fix it.

Thanks,

Lukas