How to set clock prescaler for I2S?

[kojiro_kaizuka]

We have been using MPC5645S and some sound LSI for this product is EOL. We still want to sell this product and planned to replace that sound LSI. Formerly we use 22.05KHz audio clock for I2S interface, but now we need to change the audio clock frequency to 44.1KHz.

To change audio clock configuration, I need to understand how to set proper I2S clock frequency using "I2S Clock Prescaler Register (I2SPRS)". It has two parameters, ACPSCLR and I2SPSCLR. I understand that I2SPSCLR is the divider value from the original clock but 44.1KHz cannot be generated directly dividing the original clock. I think ACPSCLR can adjust the frequency, but there are no description for this paramter in the reference manual.

Would you please tell us how ACPSCLR parameter work?

[PetrS]

Hi,

This is some explanation I found.
Calculate I2SPSCLR/ACPSCLR parameters based on I2S bit clock frequency.
The I2S bit clock frequency is the product of the sample rate, the number of bits per channel and the number of channels. So, e.g. for selected sample frequency of 44.1 kHz, with 16 bits of precision and two channels (stereo) a bit clock frequency is: 44.1 kHz × 16 × 2 = 1.411 MHz

The I2S is clocked by SGM clock (system clk/2), here max 62Mhz. 

The I2SPRS[I2SPSCLR] specifies the divide factor to achieve the bit clock. Thus I2SPRS[I2SPSCLR] = 62MHz/1.411MHz; value of 43 is selected. Generated bit clock frequency will be 1.44Mhz.

The I2SPRS[ACPSCLR] specifies the divide factor for the auxiliary clock (MCLK if enabled). If MCLK = 256*Fs and 2x16bits configuration it is 8times more than bit clock frequency thus prescaler will be 8timer smaller then I2SPSCLR; I2SPRS[ACPSCLR] = 43/8, 5 selected.

Hope it helps.

BR, Petr