Generating S19 without RAM area, MPC5602 + CW 10.2

[carlgilbert]

I'm sure this applies to any micro compiled with codewarrior 10.x.  My question is, when I generate the s19 it has RAM addresses in it.  0x4000000.  I don't want any of that in the s19 as it does not make sense to be there.  Can you tell me how to get the linker to generate the s19 without including RAM areas?

Note: It does not include all RAM areas, only some of them and I donn't know why.

Thanks

[TICS_Fiona]

First, please check the link command file in your project, which decides how to place the data and code in your project.  To understand the commands and directives in link command file, please review chapter 13 in:

http://cache.freescale.com/files/soft_dev_tools/doc/ref_manual/CWMCUPABTR.pdf

You can get detailed information for memory usage from MAP file. To generate MAP file, please click on "Project" menu->Properties ->C/C++ Build->Settings->PowerPC Linker-> Output, and enable the option "Generate Link MAP". Then rebuild the project, the MAP file will be generated under the project subfolder with <Build Target> name.

Best Regards

Fiona

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[carlgilbert]

I know a lot more now than I did then.  I agree it likely has to do with the linker.  It is putting all of my own defined sections into the s19 image.  I don't know how the linker decides what should be put in there and what should not.  How does it know that things in 'internal_ram' do not go into the s19?

does it know the names '.data' and '.sbss' etc and so it automatically does not put them into the s19?

MEMORY                                                                        

{                                                                            

    shareddata:        org = 0x40000000, len = 0x000000A0                    

    internal_ram:      org = 0x400000A0, len = 0x00002600                    

}

    GROUP :                                                                  

    {                                                                        

      .__uninitialized_intc_handlertable ALIGN(2048) : {}                    

      .data  : {}                                                            

      .sdata  : {}                                                            

      .sbss  : {}                                                            

      .sdata2 : {}                                                            

      .sbss2  : {}                                                            

      .bss    : {}                                                            

    } > internal_ram                                                          

    GROUP :                                                                  

    {                                                                        

    GLOBALDATA: {}                                  

    GLOBALDATA_2: {}                                  

    GLOBALDATA_3: {}                                  

    GLOBALDATA_4: {}                                  

    GLOBALDATA_5: {}                                  

    GLOBALDATA_6: {}                                  

    GLOBALDATA_7: {}                                  

    GLOBALDATA_8: {}                                  

    } > shareddata

Why does sharedata get put into the s19?