FreeRTOS SMP for MPC5777C

[Othmane1]

Hi,

I have a question, is it possible to use FreeRTOS SMP for MPC5777C even though I'm using two elf (each core with it's own elf)? 

i was already trying to do so but i was having problems passing the core id to the core 1 ISR as shown below:

the idea is the scheduler is triggering an interrupt on core1 (if it is free) and when i checked that when the interrupt is triggered core1 actually stops executing and goes to the ISR (below) but the priv parameter is a random value

void vPortSoftIrqISR(void *priv)

{

    BaseType_t xCore = (BaseType_t)priv;

    e_assert_void(xCore == portGET_CORE_ID());

    softirq_clear(pxSoftIRQ[xCore]);

    vTaskSwitchContext(xCore);

}

[lifepaper_cn]

Here is my "MPC5777C freertos AMP" adapting records
1.install S32D IDE and get "freertos AMP" version at C:\NXP\S32DS_Power_v2.1\S32DS\software\S32_SDK_S32PA_RTM_3.0.0\rtos\FreeRTOS_PA
2.add vPortRecursiveLock function base on bus exclusive feature
3.modify portPUSH_TASK/portPOP_TASK/portUPDATE_SYSTEM_STACK_POINTER/portLOAD_SYSTEM_STACK_POINTER, each core select different pointer address
4.read core id to r3 before call vTaskSwitchContext in vPortYield
5.different core use different heap_*.c, avoid memory using conflict
6.primary core call vTaskStartScheduler(), start scheduling

[lukaszadrapa]

Hi @Othmane1 

I think that two elf files should not be a problem but I recommend to ask directly on FreeRTOS forum about that.

Regarding the variable - isn't that caused by data cache memory? Either try to disable the cache or make sure that all shared data are forced to cache inhibited area. Another option is to enable Platform Coherency Unit PCU which maintains cache coherency between the cores.

Regards,

Lukas

[Othmane1]

I'm not using cashe memory (at least i'm not enabling it).

I continued the debug and i'm still having the problem, the weired thing is that not only i'm receiving a null pointer, also i'm not able to do any type of affectation: when i do something like var = 1, i check the var value after the afectation and var value is not changed!!!

kind regards

[lukaszadrapa]

The cache memory can be enabled by startup files. Please check DCE bit in L1CSR0 core register:

Regards,

Lukas