Floating-point division

[dariuszklibisz]

Hello,

I have some question regarding e200z4 core. I’m interested in floating-point operations and exceptions related to this operations, but the e200z4 core documentation is confusing in this regard. During division of floating point variables efsdiv assembler operation  is performed. E200z4 core documentation indicates that this operation is related to Embedded Floating-Point Unit. According to documentation FP bit in MSR register configures if:

0 - Floating-point unit is unavailable. The processor cannot execute floating-point instructions, including floating-point loads, stores, and moves. (An FP Unavailable interrupt will be generated on attempted execution of floating point instructions).

1 - Floating-point unit is available. The processor can execute floating-point instructions. (Note that for e200, the floating point unit is not supported, and an Unimplemented Operation exception will be generated for attempted execution of floating-point instructions when FP is set).

If MSR[FP] = 0, should division of floating points not be performed and “Floating-point unavailable” exception (IVOR7) should be generated or this bit matters only during attempts of execution of Book E floating point operations (efsdiv is not in Book E)?

Can e200z4 core perform division of double variables?

Best regards

[davidtosenovjan]

“Floating point unit” related to MSR[FP] is not available with e200 cores.

However floating point capability is offered by SPE unit (MSR[SPE]).

The SPE natively offers single precision floating point only. If double precision is selected it is being performed software way.

CodeWarrior generally offers following options:

‘hardware’ , ’software’ , ‘DPFP’, ‘SPFP’ and ‘SPFP only’

‘DPFP’ and ‘hardware’ options cannot be used (it‘ll lead to some exception as it would use instructions not supported by e200).

Only ’software’, ‘SPFP’ and ‘SPFP only’ can be used.

Description:

’software’ - all float operations are performed software way without SPE

‘SPFP’ - single precision uses SPE, double precision is emulated

‘SPFP only’ - retypes double format to single precision (decrease precision)

[dariuszklibisz]

So efdiv operation is executed by SPE unit even thou it should be executed by EFPU unit? Will SPE execute all EFPU unit operations? When exacly IVOR7 and IVOR32 exceptions are taken?

[davidtosenovjan]

MSR[SPE] bit is related to both, EFPU and SPE unit.

MSR[FP] is relic from other PowerPC cores variants (other then e200) its setting/clearing basically does nothing unless there is an attempt to execute unimplemented floating point instruction (for instance due to incorrect translation or other error). Then it would lead to IVOR7 (MSR[FP]=0) or IVOR6 (MSR[FP]=1).

IVOR32 is related to SPE/EFPU (if MSR[SPE]=0 and there is an attempt to execute SPE/EFPU instruction).

[jyothsnarajan]

Hi David, From your response it appears that if we use floats in programs running on e200z4 cores, by default only single precision floating point operations will be performed.

I use MPC5745 with e200z4 core and did not do anything explicit to force double precision operation, yet found that double precision operations were being executed. I had to use the compiler operation to force single precision.  This is direct contraction to your statement.  

Can you clarify "if you want double precision, it has to be done in software"? If the unit can handle only single precision, what do we gain by implementing double precision in code?

Thank you for a good discussion and explanations.

JoyR

[dariuszklibisz]

In my project MSR[FP] and MSR[SPE] are both set to 0, floating-point division is performed (efsdiv seen in debugger) and no exception is taken. Is this behaviour correct?

Sorry for being repetitive but I want to be sure.

[eguidieri]

I noticed the same behavior in my project where we are using a MCU with e200z7 core, I logged to the forum to ask how to report this.

Dariusz, for what I understood, I would call this behavior an IP Bug.

Errico