FlexCAN's FIFO function setting and question

[大大许]

Hello ,

I try to make Flexcan's message buffer[0~5] to become a fifo and to consecution receive five data frame.

compute software send five consecution data frame ,using this fifo to receive five consecutive standard data frame,and through check  interrupt  flag1 BUF6I to  check the fifo is almost full .

in my test ,i find only message buffer[0] has data ,message buffer[1~4] has no data. the interrupt flag1 bit is setting 1.

thanks

[大大许]

Hello ,

I through nxp community get an project about flexcan 

    /* subscribe FlexCAN_0's Rx FIFO for Rx - extended frame format */
    /* ID Table 0-7 */
    /* in this example we receive frames with IDE = 0x12340000 */   
    ID_Table0_CAN1 = (0x12340000<<1)|(0x40000000); /* ID(0x00000000)<<1 + EXT */
    ID_Table1_CAN1 = (0x00000000<<1)|(0x40000000); /* ID(0x00000000)<<1 + EXT */
    ID_Table2_CAN1 = (0x00000000<<1)|(0x40000000); /* ID(0x00000000)<<1 + EXT */
    ID_Table3_CAN1 = (0x00000000<<1)|(0x40000000); /* ID(0x00000000)<<1 + EXT */
    ID_Table4_CAN1 = (0x00000000<<1)|(0x40000000); /* ID(0x00000000)<<1 + EXT */
    ID_Table5_CAN1 = (0x00000000<<1)|(0x40000000); /* ID(0x00000000)<<1 + EXT */
    ID_Table6_CAN1 = (0x00000000<<1)|(0x40000000); /* ID(0x00000000)<<1 + EXT */
    ID_Table7_CAN1 = (0x00000000<<1)|(0x40000000); /* ID(0x00000000)<<1 + EXT */ 

who can tell me what is the mean.

thanks.

[PetrS]

Hi,

this code initialize full ID table. The region 0xE0-0xFC contains an 8-entry ID table that specifies filtering criteria for accepting frames into the RXFIFO.

The RXFIFO is 6-message deep. To read the RXFIFO you always use the 0x80-0x8C region, similarly as the MB0 is read. Each time you read the RXFIFO you need to clear the BUF5I flag so the FIFO output is updated with the next message.

BR, Petr

[大大许]

Hello,

I have anoher question about fifo filter setting

I try to receive standard data frame ID is the 0x7FF or extend data frame  ID is the 1FFFFFFF

#define ID_Table0_CAN0 (*(vuint32_t* )(0xffec00e0))
#define ID_Table1_CAN0 (*(vuint32_t* )(0xffec00e4))
#define ID_Table2_CAN0 (*(vuint32_t* )(0xffec00e8))
#define ID_Table3_CAN0 (*(vuint32_t* )(0xffec00eC))
#define ID_Table4_CAN0 (*(vuint32_t* )(0xffec00f0))
#define ID_Table5_CAN0 (*(vuint32_t* )(0xffec00f4))
#define ID_Table6_CAN0 (*(vuint32_t* )(0xffec00f8))
#define ID_Table7_CAN0 (*(vuint32_t* )(0xffec00fc))

ID_Table0_CAN0 = 0x3FFFFFFF;    //RTR = IDE =0;  all ID==1
ID_Table1_CAN0 = 0x3FFFFFFF;
ID_Table2_CAN0 = 0x3FFFFFFF;
ID_Table3_CAN0 = 0x3FFFFFFF;
ID_Table4_CAN0 = 0x3FFFFFFF;
ID_Table5_CAN0 = 0x3FFFFFFF;
 ID_Table6_CAN0 = 0x3FFFFFFF;
 ID_Table7_CAN0 = 0x3FFFFFFF;

CAN[nbModule]->RXFGMASK.R = 0xFFFFFFFF;

In my test ,I find this setting can't filter any data,  FIFO will receive from compute software send any data or remote frame

How should  I set my fifo filtering condition.

Thanks

[PetrS]

This should not work in the way you described, unless mask register(s) is cleared. Do you use individual or global masking scheme? And what MCU do you have in fact

As per your need the table should be

// set the ID Table, assuming CTRL2[RFFN=0] and MCR[IDAM]=0
ID_Table0_CAN0 = (0)<<30 | ((0x7FF)<<18)<<1;  // standard ID = 0x7FF
ID_Table1_CAN0 = (1)<<30 | (0x1FFFFFFF)<<1;   // extended ID = 0x1FFFFFFF
ID_Table2_CAN0 = 0;
ID_Table3_CAN0 = 0;
ID_Table4_CAN0 = 0;
ID_Table5_CAN0 = 0;
ID_Table6_CAN0 = 0;
ID_Table7_CAN0 = 0;

If global masking is used MCR[IRMQ]=0 set

CAN[nbModule]->RXFGMASK.R = 0x7FFFFFFE; // IDE and ID are checked

If individual masking is used (MCR[IRMQ]=1) then RXIMR0-7 must be initialized, similarly as the RXFGMASK.

BR, Petr