FlexCAN in MPC5746C

[Torbjörn]

I am trying to get the MPC5746C (SPC5746CSMMJ6) to work with FlexCAN and I have the following problem:

I can not setup the FlexCAN to work because when I try to set the CAN reg: CAN_3.MCR.R, I get a IVOR1 exception according to:
Exception Handling/Control Registers:
MCSR: 0x00086004
    BUS_WRERR = 1 Write bus error on buffered store to bus with DSI
    G = 1 Guarded instruction Error Report
    ST = 1 Store type instruction Error Report
    MAV = 1 MCAR Address Valid
MCAR: 0xFBEC4000

What shall I change or what have I missed to setup to make it possible to get the FlexCAN to work?

/Best regards Torbjörn

[zackwang]

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[Torbjörn]

Now after I changed MC_ME.DRUN_MC.R to 0x00130072 it is working better, getting S_MTRANS = 0 and no exception when setting CAN_3.MCR.R.

But still I can't get FlexCAN to work when I try to send a CAN message.
CAN_3.ESR1 before sending: 0x00040080 (IDLE=1 and SYNCH=1)
CAN_3.ESR1 after sending(CAN_3.MB[0].CS.B.CODE = 0xC;): 0x00284036 (ERRINT=1, BOFFINT=1, FLTCONF=3, IDLE=0, BIT0ERR=1, SYNCH=0, BOFFDONEINT=1, ERROVR=1)

/BR Torbjörn

[PetrS]

Hi,

you got bit errors, so module does not see what is transmitting. Check if CAN transceiver is enabled, proper CAN bus termination is used and MCU is connected properly to it.
Also check CAN bit timing setting.

BR, Petr

[Torbjörn]

I have fixed some pin configuration problem related to the hardware and now the CAN message transmission is working.

I am now working with CAN message reception and I can see that the CAN message is received in my selected MB (CAN_3.MB[8]) but I am not getting any interrupt. I have tried to setup CAN_3.IMASK1 for selected MB. Any idea what I missed regarding interrupts?

/BR Torbjörn

[PetrS]

Hi,

check if you did following,
- set respective bit in CAN_3.IMASK1 for selected MB
- be sure INTC is properly initialized and interrupt enabled
- assign ISR function for correct vector number (#606) in vector table
- select priority/core for interrupt in INTC_PCR[606]

BR, Petr 

[Torbjörn]

I have marked my answers with red:
- set respective bit in CAN_3.IMASK1 for selected MB - I have already setup this
- be sure INTC is properly initialized and interrupt enabled - It is based on NXP examples and should work
- assign ISR function for correct vector number (#606) in vector table - I have already setup this
- select priority/core for interrupt in INTC_PCR[606] - I think you mean INC_PSR[606]. I thought this was setup ok but now when I increased the priority to 15 it is working and I get an interrupt when receiving a CAN message.

/Best regards Torbjörn

[PetrS]

Hi,

yes, my typo. It should be INTC_PSR as you mentioned.
Then check what is a value of INTC Current Priority Register for Processor n (INTC_CPRn) at the time of INTC init. Obviously it is going to be set as the lowest, e.g.
INTC.CPR[0].B.PRI = 0; /* Lower core 0's INTC current priority to 0 */

BR, Petr

[Torbjörn · Accepted solution]

Yes the INTC Current Priority Register for Processor 0 (INTC_CPR0) is 0 at the time of INTC init (INTC.CPR0.B.PRI = 0).

I was using prio = 0 for the CAN_3 reception from the beginning and it works if I increase it to > 0.

Thanks for all help!

/BR Torbjörn

[Torbjörn]

I have used this example from the manual but never got it to work:

Example 1: Minimal Code to Bring Up a PLL:

/* F160 - max 160 MHz (/1) */
MC_CGM.SC_DC0.B.DIV = 0;

/* S80 - max 80 MHz (/2) */
/* MC_CGM_SC_DC1[DIV] and MC_CGM_SC_DC5[DIV] must be equal at all times */
MC_CGM.SC_DC1.B.DIV = 1;

/* FS80 - max 80 MHz (/2) */
/* MC_CGM_SC_DC1[DIV] and MC_CGM_SC_DC5[DIV] must be equal at all times */
MC_CGM.SC_DC5.R = MC_CGM.SC_DC1.R; /* 80 MHz max */

/* S40 - max 40 MHz (/4) */
MC_CGM.SC_DC2.B.DIV = 3;

/* F40 - max 40 MHz (/4) */
// MC_CGM.SC_DC3.B.DIV = 3; Here I am also getting a exception so I removed this line

/* F80 - max 80 MHz */
// MC_CGM.SC_DC4.B.DIV = 1; Here I am also getting a exception so I removed this line

/* enable all modes, enable all peripherals */
MC_ME.ME.R = 0x000005FF;
MC_ME.RUN_PC[0].R = 0x000000FE;

/* Connect XOSC to PLL */
MC_CGM.AC5_SC.B.SELCTL = 1;

/* Configure PLL0 Dividers - 160MHz from 40Mhx XOSC */
PLLDIG.PLLDV.B.PREDIV = 2;
PLLDIG.PLLDV.B.MFD = 32;
PLLDIG.PLLDV.B.RFDPHI = 1;
PLLDIG.PLLCAL3.R = 0x09C3C062;
PLLDIG.PLLFD.B.SMDEN = 1; /* Sigma delta modulation enabled */

/* switch to PLL */
MC_ME.DRUN_MC.R = 0x00130172; /* FLASH in normal mode, PLLON, FXOSC ON, Use PLL_PHI_0 */
MC_ME.MCTL.R = 0x30005AF0; /* DRUN target mode + KEY */
MC_ME.MCTL.R = 0x3000A50F; /* DRUN target mode + KEY Inverted */

while(0 == MC_ME.GS.B.S_PLLON); /* ME_GS Wait for PLL stabilization */
// while(1 == MC_ME.GS.B.S_MTRANS);/* Wait for mode transition complete */ Here I never got S_MTRANS to change to 0

Now when I changed MC_ME.DRUN_MC.R from 0x00130172 to 0x00130072 it works better and I can continue with setting up the FlexCAN... 

But as you can see above I still get exceptions when I try to set:
MC_CGM.SC_DC3.B.DIV = 3
MC_CGM.SC_DC4.B.DIV = 1
but it seems that this regs are setup correct anyway.

/Thanks Torbjörn

[Torbjörn]

MC_ME_PS2: 0x00020000
MC_ME_PCTL73: 0x00

To what should I setup the MC_ME_PCTL73?

I can't even read the CAN reg: CAN_3.MCR.R without getting a exception.

/BR Torbjörn

[PetrS]

Hi,

try to set 

MC_ME.RUN_PC[0].R = 0x000000FE; /* Configures peripheral clock for all RUN modes */
MC_ME.PCTL[73].B.RUN_CFG = 0x0; /* FlexCAN 3 : select peri. cfg. RUN_PC[0] */

and do mode transition, e.g. to DRUN mode

MC_ME.DRUN_MC.R = 0x00130072; /* MVRON = 1, FLAON = RUN mode, PLLON=1, FXOSCON = 1, FIRCON = 1, SYSCLK = PLL PHI_0 */
MC_ME.MCTL.R = 0x30005AF0; /* Target mode = DRUN, KEY = 5AF0 */
MC_ME.MCTL.R = 0x3000A50F; /* Target mode = DRUN, KEY = A50F */

while(MC_ME.GS.B.S_MTRANS == 1); /* Wait for mode transition complete */

BR, Petr

[PetrS]

Hi,

do you have module clocked? Check MC_ME_PS2 register and if needed configure MC_ME_PCTL73.

BR, Petr