Exception IVOR6 and IVOR33

[baimingshao]

Hello,

I have a question regarding exception IVOR6 and IVOR33 for MPC5777c. When I have a divide by 0 exception, I am expecting IVOR33, however, IVOR6 was triggered. And ESR[PIL] and ESR[VLEMI] are set. However, if I disable SPEFSCR[FDBZE], no exception is detected. So, the exception must somehow still related to divide by 0, it just IVOR33 are not triggered.

Any idea?

Thanks,

[davidtosenovjan]

Hi, do you have enabled SPE module? Check MSR register