DSPI POP Register Reading Problem

[rehan_khan]

Hello,

We are using DSPI 0 of MPC5645S device. We have configured the module as RXFIFO disable. Following are our configuration.

DSPI_0.MCR.R =0xC0020001;

DSPI_0.MCR.B.DIS_RXF = 1;

DSPI_0.MCR.B.ROOE = 1;

DSPI_0.CTAR[0].R= 0x780A7727;

DSPI_0.CTAR[0].B.CPOL=1;

DSPI_0.CTAR[0].B.CPHA=1;

DSPI_0.RSER.B.RFDF_RE = 0x1;   //enable Rx interrupt

DSPI_0.RSER.B.TCF_RE = 0x1;   //enable Tx interrupt

DSPI_0.MCR.B.HALT=0;       //start the transfers.

SIU.PCR[25].R=0x0600; //sclk0

SIU.PCR[24].R=0x0600; //sout0

SIU.PCR[23].R=0x0507; //sin0

SIU.PCR[29].R=0x0E00; //cs1_1

This  is my ISR

DSPI0ISR(void)

{  

  DSPI_0.RSER.B.RFDF_RE = 0;

  receive_dspi_data0 = (uint16_t) DSPI_0.POPR.R;

  DSPI_0.SR.R = DSPI_0.SR.R | 0x80020000;

  receive_flag0 = 1;

  DSPI_0.RSER.B.RFDF_RE = 1;

}

The problem is whenever ISR gets triggered. The data in variable receive_dspi_data0 read as zero every time even if the POP register value in debugger window shows valid data. What I have found is, this peripherals are memory mapped registers and the DSPI_0.POP is mapped to address 0xfff90038, when I look into memory window the value at this address is zero, but in debugger window it is valid data. what I observed is it takes time to see the valid data at 0xfff90038. but I cannot read the data by using DSPI_0.POPR.R in one time. That's why I am always getting zero value.

In reference manual it is written that

For compatibility, configure the TLB (MMU table) entry for DSPIx_POPR as guarded.

What does it mean. how to make DSPI_0.POP value to be read in one ISR cycle. what I can do so that value at address 0xfff90038 becomes valid data as soon program enters the receive ISR.

Please help

[davidtosenovjan]

It is nonsense to toggle RFDF_RE within interrupt service routine, it is not supposed to be there.

A "G" is provided to protect a memory space that cannot be accessed speculatively. To simplify an answer this is general recommendation for all places that may act as buffer or FIFO. My recommendation is to have cache inhibit, guarded access for all registers.

Regarding your code - I would recommend to test your code without debugger (for instance you may printf notices via terminal window) to remove possible debugger influence.

[rehan_khan]

Thanks for your reply. Earlier I was not at all using   DSPI_0.RSER.B.RFDF_RE in ISR. When things were not working I had added this.

A "G" is provided to protect a memory space that cannot be accessed speculatively. To simplify an answer this is general recommendation for all places that may act as buffer or FIFO. My recommendation is to have cache inhibit, guarded access for all registers.

can you please elaborate on this and how can I do this. what can I do for cache inhibit, guarded access for all registers.

[davidtosenovjan]

Here you can find useful tool for MMU configuration.

MMU Assist Register CONFIGURATOR

How your configuration looks like you may find out in debugger view like this: