CSE Interrupt enable not working

[Othmane1]

Hi,

I was trying to enable the interrupt for the CSE but anytime i try that my code jumps to IVOR3 and the strange part is that all the IRQq work fine except the IRQ for CSE which makes the sw jump to exception

[lukaszadrapa]

Hi @Othmane1 

Let's start from the beginning - which device do you have? Which SW drivers?
Did you check if the vector table contains correct interrupt vector? Can you see the interrupt handlet at that address? If you put a breakpoint at the first instruction of the handler, can you reach that breakpoint?
When you reach the IVOR3, what is the content of core register SRR0? This should show "Set to the effective address of the excepting instruction".

Regards,
Lukas

[Othmane1]

Hi Lukas,

which device do you have? Evaluation board for MPC5777C

Which SW drivers? cse_driver.c

Did you check if the vector table contains correct interrupt vector? Yes

Can you see the interrupt handlet at that address? If you put a breakpoint at the first instruction of the handler, can you reach that breakpoint? No because the problem in eabling the interrupt whenever i try to enable that one the sw immediately go to IVOR3

Othmane1_0-1708084205150.png

[lukaszadrapa]

What about the core register SRR0? This should help to understand from which address the core tries to fetch a code.

Regards,

Lukas

[Othmane1]

IT gives me the address of this instruction:

Othmane1_0-1708325643356.png

[lukaszadrapa]

If SRR0 really points to this command then the problem is not caused by interrupt but rather directly by store instruction.

To make it faster - is it possible to share some simplified project, so I can check it on my side?

Or maybe elf file could be sufficient - in this case, I  just need to know an address of this command. And, if possible, make sure that I can reach this command independently of your system (like call it somewhere at the beginning of main function...).

Regards,

Lukas