CMU Fault injection MPC5744P

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

CMU Fault injection MPC5744P

1,856 Views
Mennazz
Contributor II

I'm attempting to inject a fault into the CMU by setting the HFREFR and LFREFR register values to wrong values, however the CMU_ISR value is always zero.

0 Kudos
Reply
7 Replies

1,701 Views
petervlna
NXP TechSupport
NXP TechSupport

Hello,

I have got this example from application team, which is demonstrating ADC CMU.

You can give it a try,

Best regards,

Peter

0 Kudos
Reply

1,832 Views
Mennazz
Contributor II

Hello, Peter. 
The ISR is triggered successfully for CMU_1 and CMU_2. I used the same approach for CMU3 and CMU_0, but it didn't work. 
Let me explain more. 
CMU_0 desired frequency is

 
 

CMU0.png

 so I set the HFREFR to 0x1a0 and the LFREFR to 60 to trigger the ISR but it didn't work 

 

 

 

0 Kudos
Reply

1,817 Views
petervlna
NXP TechSupport
NXP TechSupport

Hello,

Hard to say. But , could you confirm your ADC / PWMs are running?

 

Untitled.png

Both are cumming from AUX0

 

Untitled.png

Best regards,

Peter

0 Kudos
Reply

1,770 Views
Mennazz
Contributor II
Yes they are both running
0 Kudos
Reply

1,757 Views
petervlna
NXP TechSupport
NXP TechSupport

Hello,

Hmm so you still see CMU ISR not set

image.png

Only thing which can prevent set up of flag is the monitor is not enabled.

I am bit confused of this whole thing as it is strait forward.

Best regards,

Peter

0 Kudos
Reply

1,744 Views
Mennazz
Contributor II

Are there any specific configurations for ADC and PWM for it to inject a fault in CMU0 and CMU3? 
knowing that I am setting:

  • CMU_3_CSR to 0x1 
  • CMU_3_HFREFR to 0x50 
  • CMU_3_LFREFR to 0x30 
  • CMU_0_CSR to 0x800301 
  • CMU0_HFREFR to 0xa0 
  • CMU_0_LFREFR to 0x60 
0 Kudos
Reply

1,847 Views
petervlna
NXP TechSupport
NXP TechSupport

Hello,

It is hard to comment from such little information.

the ISR bit is set by HW on following event. So I guess your SW doesn't no meet it.

 

Untitled.png

Best regards,

Peter

0 Kudos
Reply