Bootloader Code for the MPC5748G

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Bootloader Code for the MPC5748G

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jiteshka
Contributor I

Hi,

I am using the MPC5748G board. I have used the MPC5748G.rbf file and flashed the application using RappID And the application works.

But I want to add some functionalities in the bootloader related to the validation of the application, Can you please help me where can I find the code for the bootloader so that I can modify it to use for the purpose?

 

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jiteshka
Contributor I

Hi Lucas,

I have used SRECCONV tool and converted .srec file into alinged .s19 file. I flashed .srec file using IDE , it works fine. But, if I flash aligned .s19 file using IDE, it get flashed but it does not work.Here are the files i attached in folder.I made application to just blink two LEDs

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lukaszadrapa
NXP TechSupport
NXP TechSupport

Hi,

I’m afraid that the source files of Rappid bootloader are considered as proprietary code and it can’t be shared with customers.

There’s only an option to request another configuration (different CAN or UART interface, different speed). In this case, the bootloader is modified by our SW team and new rbf file is provided.

 

If customers want to develop own solution, we provide this application note written for MPC5748G which can be used as starting point:

https://www.nxp.com/docs/en/application-note/AN5319.pdf

https://www.nxp.com/docs/en/application-note-software/AN5319SW.zip

 

Another option is to use solutions from third parties like:

https://www.vector.com/int/en/products/products-a-z/embedded-components/flash-bootloader/

Regards,

Lukas

 

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364 Views
maharajshreekum
Contributor III

Hi Lukas,

 

Thanks for the code provided. It gave us a good starting point for writing our own BL code.

But I have an issue while writing SREC file into the flash. It doesnt get write fully. We try to read the flash area for some 200 bytes and only 100 bytes of the App srec are written.

Can you explain what the below statements mean in your code?

 

/* Select all blocks except blocks occupied by bootloader */
lowBlockSelect = 0x17C;
midBlockSelect = 0x3FE;
highBlockSelect = 0x0;
n256KBlockSelect.first256KBlockSelect = 0x003FFFFF;
n256KBlockSelect.second256KBlockSelect = 0x0;

 

How this mapping is done in terms of "0x00F8C000--0x00F8FFFF and 0x00F90000--0x00F93FFF".

 

We have provided like this:

blockSelect.lowBlockSelect = 0x100U;
blockSelect.midBlockSelect = 0x0U;
blockSelect.highBlockSelect = 0x0U;
blockSelect.first256KBlockSelect = 0x0FFFU; // Select all blocks except blocks occupied by boot-loader
blockSelect.second256KBlockSelect = 0x0U;
g_usrCnt = 0U;

 

and our BL linker is :

/* Define FLASH */
FLASH_BASE_ADDR = DEFINED(__flash_base_addr__) ? __flash_base_addr__ : 0x00FB0000;
FLASH_SIZE = DEFINED(__flash_size__) ? __flash_size__ : 160k;

/* Define SRAM */
SRAM_BASE_ADDR = DEFINED(__sram_base_addr__) ? __sram_base_addr__ : 0x40000000;
SRAM_SIZE = DEFINED(__sram_size__) ? __sram_size__ : 256K;

/* Define RAppID boot data address */
RAPPID_BOOT_APP_DELAY_ADDR = 0x00FA0008;
RAPPID_BOOT_APP_KEY_ADDR = 0x00FA000C;

MEMORY
{
flash_rchw : org = 0x00FA0000, len = 0x4
cpu0_reset_vec : org = 0x00FA0000+0x10, len = 0x4
cpu1_reset_vec : org = 0x00FA0000+0x14, len = 0x4
cpu2_reset_vec : org = 0x00FA0000+0x04, len = 0x4
rappid_boot_data : org = 0x00FA0000+0x08, len = 0x8

m_text : org = FLASH_BASE_ADDR, len = FLASH_SIZE
m_data : org = SRAM_BASE_ADDR, len = SRAM_SIZE
}

 

Please guide us where are we going wrong.

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