Accessing the memory of PRAMC_0 using MPU_0 of MPC5777C

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Accessing the memory of PRAMC_0 using MPU_0 of MPC5777C

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parth_rastogi10
Contributor III

Hi NXP,

I am working in the experiments of Multi-core scenario of MPC5777C, in which I want to do the following experiments initially which are listed below:-

  • Configure MPU such that PRAMC_0 is accessible from Core_0 but not from Core_1 of MPC5777C.
  • From Core_1 I have to access (read and write) in the memory of PRAMC_0 and see how it is behaving.

So, I request you to please guide me to achieve the above experiments.

Regards,

Parth

Parth Rastogi
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parth_rastogi10
Contributor III

Thanks for your reply lukaszadrapa

One thing I want to confirm that I want to access PRAMC_0 memory location so in the code I have added the below code for protecting the PRAMC_0 memory location:- 

/* PRAMC_0 Memory Layout */
MPU.RGD[4].WORD0.R = 0xFFF1C000; /* Start address of PRAMC_0 */
MPU.RGD[4].WORD1.R = 0xFFF1FFFF; /* End address of PRAMC_0 */
MPU.RGD[4].WORD2.R = 0x3F00001F; /* Read-write-execute allowed for all master*/
MPU.RGD[4].WORD3.R = 0x00000001; /* Mark descriptor as valid */

So, is that correct, and then I'll write to this (0xFFF1C000) memory location after reconfiguring the PRAMC_0 location from the below code:-

*(Uint32*)0xFFF1C000 = 0xAABBCCDD;/*Write any random value to PRAMC_0 */
temp = *(Uint32*)0xFFF1C000;

MPU.CESR.B.VLD = 0; /* Disable MPU */

/* Reconfigure descriptor 4 to cover PRAMC_0 except first 1KB (0xFFF1_C400‬ - 0xFFF1_FFFF) */
/* PRAMC_0 except first 1KB */
MPU.RGD[3].WORD0.R = 0xFFF1C400‬; /* Start address */
MPU.RGD[3].WORD1.R = 0xFFF1FFFF; /* End address */
MPU.RGD[3].WORD2.R = 0x3F00001F; /* Read-write-execute allowed for all master */
MPU.RGD[3].WORD3.R = 0x00000001; /* Mark descriptor as valid */

/* Cover first 1KB by descriptor 7 and disable write access for core */
/* PRAMC_0 - first 1KB */
MPU.RGD[7].WORD0.R = 0xFFF1C000; /* Start address */
MPU.RGD[7].WORD1.R = 0xFFF1C3FF; /* End address */
MPU.RGD[7].WORD2.R = 0x3F00001D; /* Read-execute allowed for all master, write not allowed for core*/
MPU.RGD[7].WORD3.R = 0x00000001; /* Mark descriptor as valid */

MPU.CESR.B.VLD = 1; /* Enable MPU*/

/* test if we can read/write address 0xFFF1_C000 */
temp = *(Uint32*)0xFFF1C000; /* This should pass because we disabled write access only */

/* This should cause bus error and trigger machine check exception because we disabled write access */
*(Uint32*)0xFFF1C000 = 0x11223344;

So, can you please tell me that I did correct??

Regards,

Parth

Parth Rastogi
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lukaszadrapa
NXP TechSupport
NXP TechSupport

Hi,

it's necessary to slightly modify the code.

First, PRAMC_0 sits below MPU_0, so you need to pick a descriptor from MPU_0 module.

Second, there are more masters on this device, so there are more configuration bits in WORD2 of the descriptor. See please description in the reference manual for more details.

Regards,

Lukas

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lukaszadrapa
NXP TechSupport
NXP TechSupport

Hi Parth,

I do not have example written directly for MPC5777C but I can provide this one:

https://community.nxp.com/docs/DOC-333962 

As you can see, the initialization code is quite simple, you just need to change the addresses and rights as needed. Important point is that all resources must be covered. Access to uncovered space results in access violation.

Regards,

Lukas

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