Thanks for your reply. Unfortunately, this didn't solve the problem. I get stuck with only one core being able to control the LEDs.
What I did:
1. I checked the AXBSx_CRSn Control Register, and the arbitration bits are at the 22 and 23 positions. These two bits need to be set to '01' for a round robin configuration
2. The registers are mapped in MPC5748G.h. There is also a mask defined in the same file. This mask (AXBS_CRS_ARB_MASK) has the value of 0x300 meaning '11 0000 0000' in binary.
3. I created a new mask that sets the two bits to '01', resulting in '01 0000 0000' in binary.
4. The default value of the CRS register's arbitration field is '00', therefore I assumed that simple bitwise OR of the old register value with the new round robin mask should do the trick.
5. I applied this to the sixth port - on the diagram you showed above the PBRIDGE_A is connected to S6
I have few questions:
1. Should I apply this mask to the CBR register of the 6th port of the AXBS type? Is that correct? does this correspond to PBRIDGE_A?
2. Should I set this register in each core of the application? I'm flashing 3 .elf files onto the board, but the Crossbar Switch can be only one. Do I need every .elf file to write this register?
3. The reference manual states that once the CRSn[RO] (first bit of the register) is set then further changes to the register are impossible. I have not been manipulating this register, so I am assuming that this bit has not bet been set.
I would be grateful for any advice.
I am including a piece of code from the MPC5748G.h and my own code.
MPC5748G.h:
/** AXBS - Register Layout Typedef */
typedef struct {
struct { /* offset: 0x0, array step: 0x100 */
__IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
uint8_t RESERVED_0[12];
__IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */
uint8_t RESERVED_1[236];
} PORT[AXBS_PORT_COUNT];
struct { /* offset: 0x800, array step: 0x100 */
__IO uint32_t MGPCR; /**< Master General Purpose Control Register, array offset: 0x800, array step: 0x100 */
uint8_t RESERVED_0[252];
} MGPCR[AXBS_MGPCR_COUNT];
} AXBS_Type, *AXBS_MemMapPtr;
/*! @name CRS - Control Register */
#define AXBS_CRS_ARB_MASK (0x300U)
my own code:
int main(void)
{
#ifdef PEX_RTOS_INIT
PEX_RTOS_INIT();
#endif
/* Initialize and configure clocks */
CLOCK_SYS_Init(g_clockManConfigsArr, (uint8_t)CLOCK_MANAGER_CONFIG_CNT, g_clockManCallbacksArr, (uint8_t)CLOCK_MANAGER_CALLBACK_CNT);
CLOCK_SYS_UpdateConfiguration(0U, CLOCK_MANAGER_POLICY_AGREEMENT);
/* set the AXBS mask for a round robin resource arbitration, necessary for multi-core LED control */
AXBS_Type AXBS_struct;
uint32_t AXBS_CRS_ARB_MASK_RR = AXBS_CRS_ARB_MASK && 0x100 ; // '01 0000 0000' for round robin
AXBS_struct.PORT[6].CRS |= AXBS_CRS_ARB_MASK_RR; // apply the mask
/* Initialize pins */
PINS_DRV_Init(NUM_OF_CONFIGURED_PINS, g_pin_mux_InitConfigArr);
/* tasks */
xTaskCreate(vBlinkLEDTask, "blinkLEDTask", 128U, NULL, 1, NULL);
vTaskStartScheduler();
for(;;) {
if(exit_code != 0) {
break;
}
}
return exit_code;
}
