MPC5xxx Knowledge Base

Discussions

******************************************************************************** * Detailed Description: * Example shows how to use original eTPU sets available over eTPU Function * Selector ( https://www.nxp.com/webapp/etpu/ ) and integrate them into * S32 Design Studio Integrated Development Platform. Example is based on * Software Development Kit (SDK) startup, in the main function adds necessary * configuration to get eTPU run. * eTPU application itself is simple PWM configured with eTPU Graphical * Configuration Tool. Target CPU is 'Generic CPU with eTPU2', eTPU clock 100MHz. * User can shows PWM waves over pins PH[10] and PH[11]. * * Tip: AN4687 may be used as reference with note the different compiler is used. * References: http://www.nxp.com/files/soft_dev_tools/doc/app_note/AN4687.pdf * https://www.nxp.com/webapp/sps/download/license.jsp?colCode=ETPUGCT * ------------------------------------------------------------------------------ * Test HW: MPC5746R-176DC Rev.A2 + MPC57xx MOTHER BOARD Rev.C * MCU: SPC5743RMLU5 QCO1640 1N83M FEAEQL * Target: Debug_FLASH * EVB connection: ETPU0_A (Port PH[10]) --> scope * ETPU1_A (Port PH[11]) --> scope * Compiler: S32DS.Power.2017.R1 * SDK release: S32_SDK_S32PA_EAR_1.8.0 * Configurator: eTPU Graphical Configuration Tool 1.4.0.4 * Debugger: Lauterbach Trace32 ******************************************************************************** Revision History: Ver Date Author Description of Changes 0.1 Apr-04-2019 David Tosenovjan Initial version *******************************************************************************/

******************************************************************************** * Detailed Description: * Application performs basic initialization, initializes interrupts, blinking * one LED by Core0, second by Core1 (by interrupt), initializes and display * notice via UART terminal and then terminal ECHO. * An example re-configures default clock setting to first and then second * configuration to shows necessary steps to perform this transtition. * * ------------------------------------------------------------------------------ * Test HW: MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU: PPC5777CMM03 2N45H CTZZS1521A * Fsys: PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH * Terminal: 19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) * ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) ********************************************************************************

******************************************************************************** * Detailed Description: * The example performs basic initialization, setup PLL to maximum allowed freq., * setup clock for peripherals, GPIO pins. * DSPI_M1 is configured as master and for DSI function to serialize eTPU channels' * outputs. eTPU to DSI routing is done by SIU configuration. * User can see SPI waveform on the scope or logic analyzer. * ------------------------------------------------------------------------------ * Test HW: MPC5746R-252DC, MPC57xx Motherboard * MCU: SPC5746RMMT5 CTQG1740 1N83M HKBGCTB * Fsys: PLL 200MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH, RAM * Terminal: 19200-8-no parity-1 stop bit-no flow control * EVB connection: connect following pins to scope or logic analyzer * PA7: DSPI_M1 SOUT (motherboard pin PP[7]) * PA9: DSPI_M1 SCLK (motherboard pin PP[9]) * PA13: DSPI_M1 CS0 (motherboard pin PP[13]) ********************************************************************************

******************************************************************************** * Detailed Description: * This example shows, how to use overlay feature - how to remap SRAM over Flash. * The remapping is visible only in mirrored flash address space. Normal address * space is not affected. * To see effect of the remapping, read the comments and watch following * addresses in debugger before and after executing Overlay() function: * * SRAM over Flash test case: * 0x4003_0000 * 0x090C_0000 * * Test HW: X-MPC5744PE257DC, MPC57xx motherboard * MCU: PPC5744PFMMM8 1N65H * Fsys: 200 MHz * Debugger: Lauterbach Trace32 * Target: internal_FLASH (debug mode, release mode) * EVB connection: none * ********************************************************************************

This document describes MPC57xx DCF (device configuration record) in details. Before MPC57xx devices can be used by application they must pass a complex system reset sequence. During system reset sequence device initialization is done. Various self-test mechanism, configuration and trimming is executed during this time. In order to prepare correct device operation, it is necessary to configure device during reset phase. For this purpose, MPC57xx implements DCF records located in special one-time programable flash memory (UTEST). To easy the work with DCF records we have created a DCF records calculators for each MPC57xx ad S32R274 device. Links to calculators: MPC5746R: https://community.nxp.com/docs/DOC-334130 MPC5777C: https://community.nxp.com/docs/DOC-335523 MPC5744P: https://community.nxp.com/docs/DOC-341538 MPC5746C: https://community.nxp.com/docs/DOC-341539 MPC5748G: https://community.nxp.com/docs/DOC-341540 MPC5775K: https://community.nxp.com/docs/DOC-341541 MPC5777M: https://community.nxp.com/docs/DOC-341542 S32R274: https://community.nxp.com/docs/DOC-341633

Detailed Description: This config tool simplifies DCF records calculation for MPC5777C device. Look at HowToUse sheet for simple guideline, then work with DCF sheet Notes: - Macros have to be enabled! - Programming more than 104 DCF records on Cut1.0b will result in incorrect device operation (FCCU faults, SSCM[CER] bit set, etc) BR, Petr

******************************************************************************** * Detailed Description: * * This example shows usage of FlexPWM module. * The Submodule0 is set to generate independent PWMA and PWMB signals * The PWMX is used as input for the Capture feature. * Capture logic is set to capture one rising and one falling edge in one shot mode. * Thus you can check the edge placing and calculate a generated duty cycle. * * ------------------------------------------------------------------------------ * Test HW: DEVKIT-MPC5744P rev.D * Maskset: 1N16P * Target : FLASH * Fsys: 200 MHz PLL1 * Debugger: Lauterbach * * * EVB connection: * * J1.3 - D[9] .. FlexPWM X[0] input * J1.5 - A[11] .. FlexPWM A[0] output * J1.7 - A[10] .. FlexPWM B[0] output * * * to measure generated pulse connect X[0] input with either A[0] or B[0] outputs. * ********************************************************************************

This example shows I2C communication with NXP PCA24S08 memory. The simple MPC5xxx I2C driver is used, see driver code/description on https://community.freescale.com/docs/DOC-330972. EVB connection: P1.11 - A[10] .. I2C0 SDA P1.12 - A[11] .. I2C0 SCL ------------------------------------------------------------------------------ Test HW: TRK-MPC5606B Maskset: 0N13E Target : RAM, Flash Terminal: 115200, 8N1 Fsys: 64 MHz PLL with 8 MHz crystal reference in RUN0. PC terminal displays this info ... You can see following I2C bus signals for particular conditions … Writing byte “H” into address 0x28 Read content of the address 0x28 Writing string “Hello world!” into address 0x152 Reading page (16 bytes) from memory address 0x150

Revision 1 of the document is now officially published: http://cache.freescale.com/files/microcontrollers/doc/app_note/AN5200.pdf http://cache.freescale.com/files/microcontrollers/doc/app_note/AN5200SW.zip Related code examples can be found also here (equal to AN5200SW): Example 1 - MPC5634M_2b_RAM_ECC_error_injection CW210 Example 2 - MPC5674F_1b+2b_RAM_ECC_error_injection CW210 Example 3 - MPC5643L 1b_RAM_ECC_error_injection CW210 Example 4 - MPC5643L 2b RAM and 2b FLASH ECC error injection CW210 Example 5 - MPC5675K-2b_RAM+2b_FLASH_ECC_error_injection CW210

* Version: 1.1 * Date: Sep-22-2021 * Classification: General Business Information * Brief: This example content a basic PMPLL initialization and * configuration of Mode Entry module and Clock Generation * module. By default active is core 2 -> e200z4 ******************************************************************************** ******************************************************************************** * Detailed Description: * ------------------------------------------------------------------------------ * Test HW: MPC57xx + S32R274RRUEVB * Maskset: 1N58R * Target : internal_FLASH * Fsys: 240 MHz PLL with 40 MHz crystal reference for z7 and 120MHz for z4 * ******************************************************************************** Revision History: 1.0 Apr-02-2019 b21190(Vlna Peter) Initial Version 1.1 Sep-22-2021 b21190(Vlna Peter) FCCU fault reading

******************************************************************************** * Detailed Description: * * Configures the MCANs to transmit and receive a CAN message. * * In this config, MCAN_1 transmits a message. MCAN_2 receives the message. * * MCAN_1 sends message each 1sec. This interval is generated by PIT. * Single TX buffer is used to send n bytes. The message ID is changed for each * transmission. Two standard and 2 extended IDs are sent. * * MCAN_2 is configured to receive a message, SW polling is used. * There are 2 standard and 2 extended ID filter tables defined. Classic filter * configuration is set, means filter ID & mask. * Messages with matched standard ID are received into RXFIFO_0, messages with matched * extended ID then stored in RXFIFO_1. * * EVB connection: * * J37 and J38 to position 1-2 to connect MCAN1 TX/RX to transceiver * * CAN0-CANH on P15-1 to CAN1-CANH on P14-1 * CAN0-CANL on P15-2 to CAN1-CANL on P14-2 * * ------------------------------------------------------------------------------ * Test HW: MPC5777M, MPC57xx Motherboard + MPC5777M_512DS minimodule * Maskset: 0N78H * Target : internal_FLASH * Fsys: 600 MHz PLL1 with 40 MHz crystal reference, * core2 at 200MHz generated from PPL1 * Terminal: None ******************************************************************************** Revision History: 1.0 Jan-5-2017 PetrS Initial Version of MCAN example *******************************************************************************/

******************************************************************************** * Detailed Description: * ------------------------------------------------------------------------------ * Test HW: MPC57xx * Maskset: 1N81M * Target : SRAM * Fsys: 160 MHz PLL * ******************************************************************************** Revision History: 1.0 Oct-29-2014 b21190(Vlna Peter) Initial Version 1.1 Nov-20-2014 b21190(Vlna Peter) Modified for Cut2.0 1.2 Nov-20-2014 b21190(Vlna Peter) Added SWT_0 dissabling in startup 1.3 Mar-10-2016 b21190(Vlna Peter) Fixed clock configuraion for PLL 1.4 Feb-23-2017 b21190(Vlna Peter) FCCU EOUT and bi-stable protocol 1.5 Aug-26-2021 nxa13250(Vlna Peter) modified for MPC5746C *******************************************************************************/

******************************************************************************** * Detailed Description: * Purpose of the example is to show how to simulate Multi-bit or Single-bit ECC * error in FlexCAN RAM (user must choose it in the option at the end of * main function). * Example configures FlexCAN module, initializes ECC for all FlexCAN RAMs, then * it injects ECC error to the Message Buffer 9. * When corrupted data is accessed the IVOR1 exception handler is called in case * of multi-bit ECC error (IVOR1 exception occurs) and FCCU_Alarm_Interrupt * handler is called in case of single-bit ECC error (FCCU interrupt occurs). * Both function calls MEMU handler. * Reported FlexCAN ECC error address is corrected according RM, section 7.12.2.3 * The example displays notices in the terminal window (connector J19 on * MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * ------------------------------------------------------------------------------ * Test HW: MPC57xx_Motherboard + MPC5744P-144DC * MCU: PPC5744PFMLQ8,0N15P,QQAA1515N, Rev2.1B * Fsys: 200 MHz PLL with 40 MHz crystal reference * Debugger: Lauterbach Trace32 * Target: internal_FLASH, RAM * Terminal: 19200-8-no parity-1 stop bit-no flow control * EVB connection: default ********************************************************************************

******************************************************************************** Detailed Description: Configures the FlexCAN_0 to transmit and receive a CAN FD message with or without bit rate switching for data phase. Baudrate during arbitration phase is set to 500kbps, during data phase 2Mpbs. NOTE! Termination resistor (120Ohm) have to be placed on transceivers output ------------------------------------------------------------------------------ Test HW: DEVKIT-MPC5748G revD1 Maskset: 0N78S Target : FLASH Fsys: 160 MHz PLL ******************************************************************************** Revision History: 1.0 Jun-21-2021 Petr Stancik Initial Version *******************************************************************************/