******************************************************************************** * Detailed Description: * Initializes eQADC module, performs calibration and cyclically converts PMC * internal channel as specified by macros CHOOSEN_PMC_ADC_CHNL, * CHOOSEN_PMC_ADC_SCALE and CHOOSEN_PMC_ADC_COMMAND to check particular voltage * level, displaying it into terminal window. * No external connection required excluding terminal via eSCI. * ------------------------------------------------------------------------------ * Test HW:         XPC567XKIT516 - MPC5674ADAT516 Rev.C, MPC567XEVBFXMB Rev.B * MCU:             PPC5674FMVYA264 * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys:            264/200/150/60 MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH, RAM * Terminal:        19200-8-no parity-1 stop bit-no flow control * EVB connection:  default ********************************************************************************

MPC5746R STCU2 configuration guide for: 1. Off-line BIST 2. On-line BIST rev 0.4

******************************************************************************** * Detailed Description: * * Example shows MCU's temperature measurement with the help of TSENS. * Calibartion constants for TSENS0/TSENS1 are read from Test flash and * eQADC is set to measure Vbg and TSENS outputs. eQADC calibration is also done. * Calculated internal temperature can be displayed on the Terminal. * * See results on PC terminal (19200, 8N1, None). You should see following text * (with different values for sure) * *    TSENS0/TSENS1 temperature measurement *     press any key to continue... * *    Calibration constants read from TSENS registers * *    TSENS0                           TSENS1 * *    TSCA_0 = 207                     TSCA_1 = 148 *    TSCB_0 = 7                       TSCB_1 = 19 * *    T = (232 + TSCA * 2^-6) * TSENS_CODE_T / VBG_CODE_T - (273 + TSCB * 2^-4) [degC] * *    VBG_CODE_T   =  997 *    TSENS0_CODE_T = 1325             TSENS1_CODE_T = 1332 * *    TSENS0 temp = 39.19 degC         TSENS1 temp = 38.86 degC * * ------------------------------------------------------------------------------ * Test HW:         MPC5777C-512DS Rev.A + MPC57xx MOTHER BOARD Rev.C * MCU:             PPC5777CMM03 2N45H CTZZS1521A * Fsys:            PLL1 = core_clk = 264MHz, PLL0 = 192MHz * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A *                  use USB connector (J21) on minimodule * EVB connection:  ETPUA30 (PortP P23-15) --> USER_LED_1 (P7-1) *                  ETPUA31 (PortP P23-14) --> USER_LED_2 (P7-2) * ********************************************************************************

******************************************************************************** * Detailed Description: * * ------------------------------------------------------------------------------ * Test HW:  TRK-MPC5634M rev.B, SPC5634M * Maskset:  1M35Y * Target :  RAM * Terminal: no * Fsys:     64 MHz PLL with 8 MHz crystal reference * * 1. you have to use an external power supply to the board (SBC power)   2. The SBC chip must be initialized (via SPI interface) to turn on the CAN transceiver.   3. For ease of use, install the VSUP shunt on (jumper J5). This it to put 9 V on the SBC's DBG pin - refer to the SBC Data Sheet for more details about the DBG pin of the SBC chip.   4. This code initializes the MCU, then sends commands to the SBC chip over the SPI bus to turn on the CAN transceiver, then the FlexCAN_A module transmits a message out of the board.   I/O configuration for the TRK-MPC5634M CAN example:   SBC_TXD  (MPC5634M CANATX PCR[83] ALT1 function) SBC_RXD  (MPC5634M CANARX PCR[84] input function)   SPI bus between the MCU and SBC:   SBC_!CS    (MPC5634M DSPI_B CS0  ALT1 function PCR[105]) SBC_CLK    (MPC5634M DSPI_B SCK  ALT1 function PCR[102]) SBC_MOSI   (MPC5634M DSPI_B SOUT ALT1 function PCR[104]) SBC_MISO   (MPC5634M DSPI_B SIN  input function PCR[103])  * ********************************************************************************

******************************************************************************** * Detailed Description: * Purpose of the example is to show how to generate Multi-bit or Single-bit ECC * error in internal FLASH (user must choose it in the option at the end of main * function). * ECC error is injected by reading of pre-defined patterns in UTEST area at * addresses 0x00400040 and 0x00400060. * When corrupted data is accessed the IVOR1 exception handler is called in case * of multi-bit ECC error (IVOR1 exception occurs) and FCCU_Alarm_Interrupt * handler is called in case of single-bit ECC error (FCCU interrupt occurs). * Both function calls MEMU handler. * The example displays notices in the terminal window (connector J19 on * MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * ------------------------------------------------------------------------------ * Test HW:         MPC57xx_Motherboard + MPC5744P-144DC * MCU:             PPC5744PFMLQ8,0N15P,QQAA1515N, Rev2.1B * Fsys:            200 MHz PLL with 40 MHz crystal reference * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH, RAM * Terminal:        19200-8-no parity-1 stop bit-no flow control * EVB connection:  default ********************************************************************************

******************************************************************************** * Detailed Description: * This example demostrates how to configure CGM )clock generation module) * and supply by clock all main peripherals. * Example demonstrate FCCU fake fault injection for fault 7 amd Alarm state * interrupt calling after injecting fake fault 7. * ------------------------------------------------------------------------------ * Test HW:  MPC57xx EVB * Maskset:  0N50N * Target :  internal_FLASH * Fsys:     200 MHz PLL * ******************************************************************************** Revision History: 1.0     Nov-04-2014     b21190(Vlna Peter)  Initial Version 1.1     Feb-04-2016     b21190(Vlna Peter)  Fixed Clock configuration 1.2    Jun-16-2017    b21190(Vlna Peter)  FCCU fake fault injection 1.3    Jun-16-2017    b21190(Vlna Peter)  FCCU alarm interrupt example *******************************************************************************/

******************************************************************************** * Detailed Description: * * Configures the FlexCANs to transmit and receive a CAN FD message with or without * bit rate switching for data phase. * Baudrate during arbitration phase is set to 500kbps, during data phase 2Mpbs. * * In this config, CAN_0 transmits a message. CAN_1 receives the message. * * EVB connection: * * CAN0-CANH on P15-1 to CAN1-CANH on P14-1 * CAN0-CANL on P15-2 to CAN1-CANL on P14-2 * * NOTE! Termination resistor (120Ohm) have to be placed on transceivers output * * ------------------------------------------------------------------------------ * Test HW:  X-MPC574xG-324DS + X-MPC574XG-MB * Maskset:  1N81M * Target :  FLASH * Fsys:     160 MHz PLL * ********************************************************************************

******************************************************************************** * Detailed Description: * MPU is initialized to cover all resources (flash, RAM, peripheral bridges). * All masters are allowed to read-write-execute from all resources. * * Simple test case is used to check the behavior of MPU in case of access * violation: * - the MPU is reconfigured to disable write access to first 1KB or RAM memory *   (0x4000_0000 - 0x4000_03FF). * - if we write this RAM area, machine check exception is triggered * ------------------------------------------------------------------------------ * Test HW:         XPC567XKIT516 - MPC5674ADAT516 Rev.C, MPC567XEVBFXMB Rev.B * MCU:             PPC5674FMVYA264 * Fsys:            264MHz * Debugger:        Lauterbach Trace32 * Target:          RAM, internal_FLASH * ********************************************************************************

******************************************************************************** * Version:          1.0 * Date:             Oct-22-2014 * Classification:   General Business Information * Brief:        This example demonstrate SWT functionality *                 On SWT timeout it sent signal to FCCU where is long *                 functional reset reaction on SWT timeout configured *                 FCCU then sent signal to RGM module which triggers long *                 functional reset. ******************************************************************************** * Test HW:  MPC57xx * Maskset:  1N65H * Target :  internal_FLASH * Fsys:     200 MHz PLL with 40 MHz crystal reference ******************************************************************************** Revision History: 1.0     Oct-22-2014     b21190(Vlna Peter)  Initial Version 1.1     Mar-24-2015    b21190(Vlna Peter)  Added SWT long reset *******************************************************************************/

******************************************************************************** * Detailed Description: * This example content a basic PMPLL initialization and *  configuration of Mode Entry module and Clock Generation *  module for core1 and start of core0 and core0s from Core_Init function. * Also containts Lauterbach multicore multi-Trace32 view script for multicore * debugging puproses ******************************************************************************** * Test HW:  Test HW:  MPC57xx Motherboard + MPC5777M_512DS minimodule, MPC5777M, * Test HW:  MPC57xx * Maskset:  1N83M (cut 2.0B) * Target :  internal_FLASH * Fsys:     200MHz PLL0 as system clock ******************************************************************************** Revision History: 1.0     Jun-09-2015     b21190(Vlna Peter)  Initial Version 1.1     Sep-20-2016     b21190(Vlna Peter)  core0+core0s boot function added *******************************************************************************

******************************************************************************** * Detailed Description: * Basic initialization of CMPU: * Region 0 (Instruction): Internal Flash @ 0x0040_0000-0x01FF_FFFF * Region 1 (Instruction): SRAM   @ 0x4000_0000-0x4005_FFFF * Region 6 (Data): SRAM @ 0x4000_0000-0x4005_FFFF * Region 7 (Data): Internal Flash @ 0x0040_0000-0x011F_FFFF * Region 8 (Data): PBRIDGE1/0 @ 0xF800_0000-0xFFFF_FFFF * * This excel configurator has been used: * https://community.nxp.com/docs/DOC-335467 * * ------------------------------------------------------------------------------ * Test HW:         X-MPC5744PE257DC, MPC57xx motherboard * MCU:             PPC5744PFMMM8 1N65H * Fsys:            200 MHz PLL * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * start one Z7 core, interrupts initialization, ICache and DCache are disabled * on both cores because of shared memory, which must not be cached. * * There is 4K shared memory defined in the linker file. This memory is used by * both cores. Both cores access into the structure, which is placed in the shared * memory. This access is marked as a critical section. Only one core can write * to the structure at the same time. To ensure this, there are Gates, which * guarantee data coherence during the access. Only one core can be in critical * section. Second core has to wait, until first core leaves the critical section * * * * ------------------------------------------------------------------------------ * Test HW:         MPC5775K-356DS, MPC57xx Motherboard * MCU:             PPC5775KMMY3B 0N76P * Terminal:        19200-8-no parity-1 stop bit-no flow control on LINFlexD_0 * Fsys:            PLL0 266MHz *                    Z4 Core 133MHz *                    Z7 Core 266MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  default connection * ********************************************************************************

******************************************************************************** * Detailed Description: * Initializes eQADC module, converts specified command queue and displays * results into terminal window when EOQ is reached. Used analog inputs ANA_0 and * ANA_1 requires external connection to converted voltage (potentiometer) to * see some valid numbers. For simplicity, ADC module is not calibrated. * ------------------------------------------------------------------------------ * Test HW:         XPC567XKIT516 - MPC5674ADAT516 Rev.C, MPC567XEVBFXMB Rev.B * MCU:             PPC5674FMVYA264 * Terminal:        19200-8-no parity-1 stop bit-no flow control on eSCI_A * Fsys:            264/200/150/60 MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          RAM, internal_FLASH * EVB connection:  Potentiometers     --> ADC inputs *                  USER_DEV_RV2(J4-7) --> ANA_0 (J18-3) *                  USER_DEV_RV3(J4-8) --> ANA_1 (J18-4)                * ********************************************************************************

This document gives a basic insight into bit timings relationship and provide easy step-by-step guide to calculate CAN bit timing parameters for desired baudrate.

******************************************************************************** * Detailed Description: * This example content a driver for CGM module configuration. * ------------------------------------------------------------------------------ * Test HW:  MPC57xx Motherboard + MPC5744PE257DC minimodule, MPC5744P, * silicon mask set 1N65H * Target :  internal_FLASH* ********************************************************************************

******************************************************************************** * Detailed Description: * Purpose of the example is to show how to generate EDC after ECC error in * internal FLASH. Error response in achieved by reading of pre-defined patterns * in UTEST area at address 0x00400080 which generates IVOR1 exception and FCCU * interrupt (FCCU_Alarm_Interrupt). * Example does not show any handling as it is application specific. * The example displays notices in the terminal window (connector J19 on * MPC57xx_Motherboard)(19200-8-no parity-1 stop bit-no flow control on eSCI_A). * No other external connection is required. * ------------------------------------------------------------------------------ * Test HW:         MPC57xx_Motherboard + MPC5744P-144DC * MCU:             PPC5744PFMLQ8,0N15P,QQAA1515N, Rev2.1B * Fsys:            200 MHz PLL with 40 MHz crystal reference * Debugger:        Lauterbach Trace32 * Target:          internal_FLASH, RAM * Terminal:        19200-8-no parity-1 stop bit-no flow control * EVB connection:  default ********************************************************************************

******************************************************************************** * Detailed Description: * Initializes eQADC module, performs calibration and converts channel 146 * (voltage level of VDD) to check core voltage level and displays it into * terminal window. No external connection required excluding terminal via eSCI. * * ------------------------------------------------------------------------------ * Test HW:        XPC564AKIT208S and XPC564AKIT324S * MCU:            SPC5644AMMG1,0M14X and SPC5644AMVZ1,0M14X * Fsys:           150/132/120/12 MHz * Debugger:       Lauterbach Trace32 *                 PeMicro USB-ML-PPCNEXUS * Target:         RAM, internal_FLASH * Terminal:       19200-8-no parity-1 stop bit-no flow control on eSCI_A * EVB connection: default * ********************************************************************************

A requirement of the standard is to detect the accumulation of latent defects. To meet this requirement the MPC5744P has the ability to execute Built-In Self-Test (BIST) procedures.

******************************************************************************** * Detailed Description: * * Application initializes SPI0 module as a master and SPI2 module as a slave. * Data are sent from master to slave and from slave to master. After data are * received, interrupt for each module is handled and data are saved to global * variables. * * * ------------------------------------------------------------------------------ * Test HW:         MPC5775K-356DS, MPC57xx Motherboard * MCU:             PPC5775KMMY3A 0N76P * Fsys:            PLL0 266MHz *                    Z4 Core 133MHz * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Target:          internal_FLASH (debug mode, release mode) * EVB connection:  P18.0 to P18.5 (CS_0) *                    P18.2 to P18.7 (SCK) *                    P18.3 to P18.9 (SIN - SOUT) *                    P18.4 to P18.8 (SOUT - SIN) * * ********************************************************************************

******************************************************************************** * Detailed Description: * Application performs basic initialization, setup PLL to maximum allowed freq., * initializes interrupts, blinking one LED by interrupt, third LED by software * loop, initializes and display notice via UART terminal and then terminal ECHO. * Second core is started and second LED blinking is being performed by it. * The example configures the device for maximum performance (OPTIMIZATIONS_ON) * by initialization of instruction cache and enabling of branch prediction. * Example suppose MCU is configured for DPM (Decoupled-parallel mode). * Its intention is to offer advanced startup code additional to CW stationery. * * ------------------------------------------------------------------------------ * Test HW:         xPC564xLKIT, PPC5643L Cut3 silicon * Target :         internal_FLASH, RAM * Fsys:            120 MHz PLL0 * Debugger:        Lauterbach Trace32 *                  PeMicro USB-ML-PPCNEXUS * Terminal:        19200-8-no parity-1 stop bit-no flow control via LINFlex0 * EVB connection:  default * ********************************************************************************