Example MPC5746R FCCU Alarm State GHS716

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Example MPC5746R FCCU Alarm State GHS716

Example MPC5746R FCCU Alarm State GHS716

* File:                 main.c
* Owner:            Peter Vlna
* Version:           1.7
* Date:               Oct-10-2017
* Classification: General Business Information
* Brief:                Example contains startup with PLL0 200MHz as system clock
*                          and demonstrates reset triggered on FCCU Alarm state
*                          counter exppire.
* Test HW:  MPC57xx
* Maskset:  1N83M (cut 2.0B)
* Target :  internal_FLASH
* Fsys:     200MHz PLL0 as system clock
Revision History:
1.0     Oct-19-2015     Peter Vlna   Initial Version
1.1    Nov-11-2015    Peter Vlna   Added PPL0 200MHz as system clock
1.2    Dec-02-2015    Peter Vlna  Added Flash controller init
1.3    Dec-02-2015    Peter Vlna  Fixed system clock init
1.4    Feb-07-2017    Peter Vlna  SWT0 and SWT1 disabled in startup
1.5     May-31-2017    Peter Vlna  Fixed comments in AC6 (CLKOUT)
1.6     Oct-04-2017    Peter Vlna  Added PIT + Interrupts
1.7    Oct-05-2017    Peter Vlna  FCCU EOUT test in Alarm state with SMC



Hi Peter,

In this example, you are using the functional muxing (MSCR registers) to confiure FCCU EOUT_0/1 pins as below. 

   SIUL2.MSCR0_255[112].R = 0x6|0x02000000;     /* FCCU EOUT_0 , ODC push-pul */
   SIUL2.MSCR0_255[115].R = 0x6|0x02000000;     /* FCCU EOUT_1 , ODC push-pul */

However, the recommended way to do this configuration is by DCF clients. -- Chapter 1.2.10 DCF_ERROR0_PAD_SELECT DCF client, MPC5746R Reference Manual Addendum, Rev. 2, 10/2016.  What's more, in the attached (in RM) "IO_Signal_Description and Input_Multiplexing_Tables", ERRORx is not listed as a muxing function which can be assigned to these potential ERROR OUT pins like PH[0] via SIUL2_MSCR registers.

Best Regards


FCCU EOUT 这个问题,您解决了吗,方便告知下关键点吗

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Last update:
‎09-24-2018 06:18 AM
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