rpmsg-lite porting on our MCU(RISC-V platform )

[yzs]

hello，

          I have a question about rpmsg-lite porting: Is it possible to use rpmsg-lite to encapsulate the mailbox as shared memory? That is, if there is only a small amount of data (e.g. less than 256 bytes), the mailbox will be used as shared memory to transfer the data, and if the data is larger than 256 bytes, it will still use the original shared memory used by rpmsg-lite, but it will still use the original API interface to initialize, create endpoints, and send the data (which may involve modifying the code). Is this approach feasible?

#rpmsg-lite #FDRM-MCXN947SDK 

[Harry_Zhang]

Hi @yzs 

Yes, your approach is indeed feasible, and it’s possible to modify the rpmsg-lite framework to utilize the mailbox as shared memory for small data transfers, while still falling back to traditional shared memory for larger transfers.

BR

Harry

[yzs]

Hi, @Harry_Zhang
        Thanks for answering question. My idea is to modify to point the buffer address of desc.addr to mailbox, but desc, avail, used in vring are still maintained in shared memory, is this possible? Because considering the limited space in mailbox, just 256 Bytes.

Thanks & Regards

yzs

[Harry_Zhang · Accepted solution]

Hi @yzs 

Yes, i think your approach is feasible. The buffer address (desc.addr) in a Virtio ring (vring) can point to a different memory region, such as a mailbox, while the desc, avail, and used structures remain in shared memory.

BR

Harry

[yzs]

hi,

        Thanks. In the demo of multicore rpmsg-lite pingpong communication using the SDK for the FRDM-MCXN947 board, I found that after the master core bootstraps the remote core to start, the remote core does rpmsg_lite_remote_init() first, then notifies the master core, and then the remote core waits for connection (rpmsg_lite_wait_for_ link_up()). During this time the master core waits (while()). After the master core is initialized rpmsg_lite_master_init(), the remote core makes the connection and creates the endpoint, then notifies the master that it is ready to send data. In use, I commented out the notification as well as the wait code and found that the master and remote cores can also link-up and communicate, what is the reason for this? Is it because the master system clock is slower than the remote ?
        In addition, I would like to ask, if our MCU does not have such a notification mechanism, how to ensure that the master and slave cores are link-up and can communicate?

Thanks & Regards

yzs