i.MX8MM DDR Tool (Config Tools 25.12) – UART Communication Timeout

[suraj02]

I working on a custom board based on MIMX8MM4DVTLZAA using Config Tools for i.MX (v25.12, DDR Tool v3.30) for DDR3 validation.

Setup:

• DDR: K4B4G1646D-BYK0 (single chip)

• Boot: SDP (USB)

• UART used: UART2 (USB-UART, 115200)

Observation:

• SDP download & jump → OK

• Board executes image → OK

• UART logs visible on terminal:

  hardware_init...
  DDR frequency 800MHz

• But DDR tool fails during phy_init with:

  • Timeout waiting for “[TARGET IS ALIVE]”

  • “Application is not waiting for input state”

Issue:
Tool cannot establish handshake, although UART prints logs.
I check with older tool v3.30, with that getting this Waiting for board configuration from PC-end... after hardware init, but after this there is nothing is coming.

Question:
How to resolve above issue?

Attachmets:
- DDR config screenshot
- .ds (changed to .txt for upload)

[suraj02]

The issue is now resolved using mscale_ddr_tool_v3.31. DDR calibration and stress tests are being completed successfully.

The root cause of Invalid Target(Request=0x0, CoreID=0xd03) issue was mainly related to UART communication on the hardware side. After properly re-soldering the UART connections and making minor adjustments in the .ds script, the DDR tool started working as expected. We also referred to the below thread and used the older tool version (v3.31):
https://community.nxp.com/t5/i-MX-Processors/iMX8M-Plus-LPDDR4-Config-Tool-failure/m-p/1979486

However, with the latest Config Tools fori.MX (v25.12), we are still facing the same issue (UART timeout during phy_init).:

• Timeout waiting for “[TARGET IS ALIVE]”

• “Application is not waiting for input state”

[suraj02]

I would like to share a brief update on the DDR validation issue shared above, for our custom board based on the MIMX8MM4DVTLZAA.
What we tried:
• Initially faced timeout issue with Config Tools (25.12):
“Timeout waiting for [TARGET IS ALIVE]”
• Based on forum reference:
https://community.nxp.com/t5/i-MX-Processors/iMX8M-Plus-LPDDR4-Config-Tool-failure/m-p/1979486
we tried older DDR Stress Tool (v3.31).
• Tool was stuck at “Waiting for board configuration from PC-end...”
→ Fixed by moving PMIC init block to the start of .ds script.
• After this, board responds correctly and DDR configuration is detected.
Current Issue:
• Now failing with:
Invalid Target(Request=0x0, CoreID=0xd03)
• Reference to similar issue:
https://community.nxp.com/t5/i-MX-Processors/LPDDR4-issue-in-DDR-Stress-Tool/m-p/1163159
Checks done:
Correct target (i.MX8MM) selected
PMIC configuration working
All required voltages (VDD_SOC, VDD_ARM, etc.) verified
Current Logs (snippet):
Downloading file 'bin\ddr3_train_string_v201709.bin' ..Done

Downloading file 'bin\ddr3_imem_1d_v201709.bin' ..Done

Downloading file 'bin\ddr3_dmem_1d_v201709.bin' ..Done

Downloading IVT header...Done
Downloading file 'bin\m845s_ddr_stress_test.bin' ...Done

Download is complete
Waiting for the target board boot...

===================hardware_init=====================
PMIC is initialized in DDR script
Write 0x0 to PMIC reg[0xc] successfully
Write 0x14 to PMIC reg[0x11] successfully
Write 0x20 to PMIC reg[0x14] successfully
Write 0x14 to PMIC reg[0x17] successfully
Write 0x6c to PMIC reg[0x1a] successfully
Write 0x30 to PMIC reg[0x1c] successfully
Write 0x1e to PMIC reg[0x1e] successfully
Write 0xc0 to PMIC reg[0x21] successfully
Write 0xc0 to PMIC reg[0x22] successfully
Write 0xc0 to PMIC reg[0x23] successfully
Write 0xc1 to PMIC reg[0x24] successfully
Write 0xc0 to PMIC reg[0x25] successfully
hardware_init exit

*************************************************************************

*************************************************************************

*************************************************************************
MX8 DDR Stress Test V3.30
Built on Nov 24 2021 13:30:14
*************************************************************************

Waiting for board configuration from PC-end...

--Set up the MMU and enable I and D cache--
- This is the Cortex-A53 core
- Check if I cache is enabled
- Enabling I cache since it was disabled
- Push base address of TTB to TTBR0_EL3
- Config TCR_EL3
- Config MAIR_EL3
- Enable MMU
- Data Cache has been enabled
- Check system memory register, only for debug

- VMCR Check:
- ttbr0_el3: 0x93d000
- tcr_el3: 0x2051c
- mair_el3: 0x774400
- sctlr_el3: 0xc01815
- id_aa64mmfr0_el1: 0x1122

- MMU and cache setup complete

*************************************************************************
ARM clock(CA53) rate: 1800MHz
DDR Clock: 800MHz

============================================
DDR configuration
DDR type is DDR3
Data width: 16, bank num: 8
Row size: 15, col size: 10
One chip select is used
Number of DDR controllers used on the SoC: 1
Density per chip select: 512MB
Density per controller is: 512MB
Total density detected on the board is: 512MB
============================================

Invalid Target(Request=0x0, CoreID=0xd03)

*************************************************************************
Question:
How to resolve this Invalid Target issue, on what should i focus on?

[pengyong_zhang]

Hi @suraj02 

Is your board in download mode?

B.R

[suraj02]

Yes I checked that, its in download mode:
$ ./uuu.exe -lsusb
uuu (Universal Update Utility) for nxp imx chips -- libuuu_1.5.243-0-g230f1b1

Connected Known USB Devices
Path Chip Pro Vid Pid BcdVersion Serial_no
====================================================================
1:1 MX8MM SDP: 0x1FC9 0x0134 0x0101